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author | Tristan Gingold <tgingold@free.fr> | 2020-03-10 19:26:20 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-10 19:26:20 +0100 |
commit | c7fc6185ae789e248c0752577ca44e6100616399 (patch) | |
tree | 9caa4eed4951ff38a523822073571d6c89ac4c91 /testsuite/synth/slice02/slice02.vhdl | |
parent | 3ea034dfb17430430b49000f4d9e4d54032e4b3e (diff) | |
download | ghdl-c7fc6185ae789e248c0752577ca44e6100616399.tar.gz ghdl-c7fc6185ae789e248c0752577ca44e6100616399.tar.bz2 ghdl-c7fc6185ae789e248c0752577ca44e6100616399.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/slice02/slice02.vhdl')
-rw-r--r-- | testsuite/synth/slice02/slice02.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/slice02/slice02.vhdl b/testsuite/synth/slice02/slice02.vhdl new file mode 100644 index 000000000..6c78f67bf --- /dev/null +++ b/testsuite/synth/slice02/slice02.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity slice02 is + port (di : std_logic_vector(7 downto 0); + do : out std_logic_vector (3 downto 0)); +end slice02; + +architecture behav of slice02 is + type mem is array (natural range <>) of std_logic_vector (1 downto 0); + signal m1, m2 : mem (3 downto 0); +begin + m1 <= (di (7 downto 6), di (5 downto 4), di (3 downto 2), di (1 downto 0)); + m2 <= m1 (0 downto 0) & m1 (1 downto 1) & m1 (2 downto 2) & m1 (3 downto 3); + do <= m2 (1) & m2 (0); +end behav; |