testsuite/synth: add a test for inout variable

1 files changed, 23 insertions, 0 deletions

diff --git a/testsuite/synth/subprg01/subprg01.vhdl b/testsuite/synth/subprg01/subprg01.vhdl
new file mode 100644
index 000000000..9a21cbb8c
--- /dev/null
+++ b/testsuite/synth/subprg01/subprg01.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity subprg01 is
+  port (a : std_logic_vector (3 downto 0);
+        na : out std_logic_vector (3 downto 0));
+end subprg01;
+
+architecture behav of subprg01 is
+  procedure neg (v : inout std_logic_vector(3 downto 0)) is
+  begin
+    v := not v;
+  end neg;
+
+begin
+  process(A)
+    variable t : std_logic_vector(3 downto 0);
+  begin
+    t := a;
+    neg (t);
+    na <= t;
+  end process;
+end behav;