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author | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:38:32 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:38:32 +0100 |
commit | 0692c627a4bde8715e86b6dc1b6e55c8cdb10d76 (patch) | |
tree | 19869f0c71a30ae7fa654328879f35b72f291e1d /testsuite/synth/subprg01/tb_subprg02.vhdl | |
parent | 365d6b03e6045059c2813fe24204ee0b6e571045 (diff) | |
download | ghdl-0692c627a4bde8715e86b6dc1b6e55c8cdb10d76.tar.gz ghdl-0692c627a4bde8715e86b6dc1b6e55c8cdb10d76.tar.bz2 ghdl-0692c627a4bde8715e86b6dc1b6e55c8cdb10d76.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/subprg01/tb_subprg02.vhdl')
-rw-r--r-- | testsuite/synth/subprg01/tb_subprg02.vhdl | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/synth/subprg01/tb_subprg02.vhdl b/testsuite/synth/subprg01/tb_subprg02.vhdl new file mode 100644 index 000000000..0736990a7 --- /dev/null +++ b/testsuite/synth/subprg01/tb_subprg02.vhdl @@ -0,0 +1,37 @@ +entity tb_subprg02 is +end tb_subprg02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_subprg02 is + signal a, na : std_logic_vector (3 downto 0); + signal n : natural range 0 to 1; + signal clk : std_logic; +begin + dut: entity work.subprg02 + port map (a, n, clk, na); + + process + procedure pulse is + begin + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + clk <= '0'; + end pulse; + begin + n <= 0; + clk <= '0'; + + a <= x"0"; + pulse; + assert na = x"f" severity failure; + + a <= x"5"; + pulse; + assert na = x"a" severity failure; + + wait; + end process; +end behav; |