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authorTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
commit6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch)
tree12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/synth34/tb_repro_uns.vhdl
parentdcc353b07b82a84f2aa598de3884c58f406e0652 (diff)
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testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/synth34/tb_repro_uns.vhdl')
-rw-r--r--testsuite/synth/synth34/tb_repro_uns.vhdl35
1 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/synth/synth34/tb_repro_uns.vhdl b/testsuite/synth/synth34/tb_repro_uns.vhdl
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+++ b/testsuite/synth/synth34/tb_repro_uns.vhdl
@@ -0,0 +1,35 @@
+entity tb_repro_uns is
+end tb_repro_uns;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_repro_uns is
+ signal clk : std_logic;
+ signal a : unsigned(7 downto 0);
+ signal b : unsigned(7 downto 0);
+begin
+ dut: entity work.repro_uns
+ port map (
+ clk => clk, a => a, b => b);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ a <= x"ab";
+ pulse;
+ assert b = x"ab" severity failure;
+
+ a <= x"12";
+ pulse;
+ assert b = x"12" severity failure;
+ wait;
+ end process;
+end behav;