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author | Tristan Gingold <tgingold@free.fr> | 2020-01-01 21:14:55 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-01 21:14:55 +0100 |
commit | 669dc74413a1b263f3377503d1b2703884550290 (patch) | |
tree | 46489a6fc64e9793ebfd4aaa3cb05b13b9dad3af /testsuite/synth/synth38/tb_modulo_test.vhdl | |
parent | 4defa9eaf8694042abc1fb87dc957c7b6a0e56f9 (diff) | |
download | ghdl-669dc74413a1b263f3377503d1b2703884550290.tar.gz ghdl-669dc74413a1b263f3377503d1b2703884550290.tar.bz2 ghdl-669dc74413a1b263f3377503d1b2703884550290.zip |
testsuite/synth: improve test for previous commit.
Diffstat (limited to 'testsuite/synth/synth38/tb_modulo_test.vhdl')
-rw-r--r-- | testsuite/synth/synth38/tb_modulo_test.vhdl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/synth/synth38/tb_modulo_test.vhdl b/testsuite/synth/synth38/tb_modulo_test.vhdl new file mode 100644 index 000000000..0395be47a --- /dev/null +++ b/testsuite/synth/synth38/tb_modulo_test.vhdl @@ -0,0 +1,31 @@ +entity tb_modulo_test is +end tb_modulo_test; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_modulo_test is + signal a, b, c : integer := 0; +begin + dut: entity work.modulo_test + port map (a, b, c); + + process + begin + a <= 7; + wait for 1 ns; + assert b = 7 severity failure; + assert c = 7 severity failure; + + a <= 8; + wait for 1 ns; + assert b = 0 severity failure; + assert c = 0 severity failure; + + a <= -7; + wait for 1 ns; + assert b = 1 severity failure; + assert c = -7 severity failure; + wait; + end process; +end behav; |