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authorTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
commit6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch)
tree12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/synth40/tb_testcase.vhdl
parentdcc353b07b82a84f2aa598de3884c58f406e0652 (diff)
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testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/synth40/tb_testcase.vhdl')
-rw-r--r--testsuite/synth/synth40/tb_testcase.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/synth40/tb_testcase.vhdl b/testsuite/synth/synth40/tb_testcase.vhdl
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index 000000000..3ed89e61c
--- /dev/null
+++ b/testsuite/synth/synth40/tb_testcase.vhdl
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+entity tb_testcase is
+end tb_testcase;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_testcase is
+ signal di : std_logic;
+ signal do : std_logic;
+begin
+ dut: entity work.testcase
+ port map (data_in => di, data_out => do);
+
+ process
+ begin
+ di <= '1';
+ wait for 1 ns;
+ assert do = '0' severity failure;
+
+ di <= '0';
+ wait for 1 ns;
+ assert do = '1' severity failure;
+
+ wait;
+ end process;
+end behav;