aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/synth/synth8/vector8_test1.vhdl
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
commit6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch)
tree12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/synth8/vector8_test1.vhdl
parentdcc353b07b82a84f2aa598de3884c58f406e0652 (diff)
downloadghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.tar.gz
ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.tar.bz2
ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.zip
testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/synth8/vector8_test1.vhdl')
-rw-r--r--testsuite/synth/synth8/vector8_test1.vhdl16
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/synth8/vector8_test1.vhdl b/testsuite/synth/synth8/vector8_test1.vhdl
new file mode 100644
index 000000000..585d003b0
--- /dev/null
+++ b/testsuite/synth/synth8/vector8_test1.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector8_test1 is
+ port (led7: out std_logic);
+end vector8_test1;
+
+architecture synth of vector8_test1 is
+
+signal v : std_logic_vector(7 downto 0);
+
+begin
+ v(7) <= '1';
+ led7 <= v(7);
+end synth;