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authorTristan Gingold <tgingold@free.fr>2020-01-13 18:55:13 +0100
committerTristan Gingold <tgingold@free.fr>2020-01-13 18:55:13 +0100
commita7fc811243abef3bd4428c3368e7ae5b105322a0 (patch)
tree767ed52b9df20279d0e5503db5f05cee335474da /testsuite/synth/uassoc01/uassoc02.vhdl
parent6fe2bb0bc0889ddf3fa905d4563f9c72a7230987 (diff)
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testsuite/synth: add test for previous commit.
Diffstat (limited to 'testsuite/synth/uassoc01/uassoc02.vhdl')
-rw-r--r--testsuite/synth/uassoc01/uassoc02.vhdl39
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/uassoc01/uassoc02.vhdl b/testsuite/synth/uassoc01/uassoc02.vhdl
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+++ b/testsuite/synth/uassoc01/uassoc02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uassoc02_sub is
+ port (i : std_logic_vector;
+ o : out std_logic_vector);
+end uassoc02_sub;
+
+architecture behav of uassoc02_sub is
+begin
+ o <= not i;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uassoc02 is
+ port (i1 : std_logic_vector(3 downto 0);
+ i2 : std_logic_vector(7 downto 0);
+ o : out std_logic_vector(3 downto 0));
+end uassoc02;
+
+architecture rtl of uassoc02 is
+ component uassoc02_sub is
+ port (i : std_logic_vector;
+ o : out std_logic_vector);
+ end component;
+
+ signal o1: std_logic_vector(3 downto 0);
+ signal o2: std_logic_vector(7 downto 0);
+begin
+ dut1: uassoc02_sub
+ port map (i => i1, o => o1);
+
+ dut2: uassoc02_sub
+ port map (i => i2, o => o2);
+
+ o <= o1 xor o2 (3 downto 0);
+end rtl;