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authorTristan Gingold <tgingold@free.fr>2019-09-17 02:18:41 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-17 02:18:41 +0200
commitde899bb8cb6e2f43a3e80a6a273d6a459b08e401 (patch)
treee44c55c459c9a1fe5814103927d7ac8be4f8a40e /testsuite/synth/var01/tb_var04.vhdl
parentb7a36d7d7838d05b449aa7e23935cd0e3e4213d4 (diff)
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testsuite/synth: add var01
Diffstat (limited to 'testsuite/synth/var01/tb_var04.vhdl')
-rw-r--r--testsuite/synth/var01/tb_var04.vhdl38
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/var01/tb_var04.vhdl b/testsuite/synth/var01/tb_var04.vhdl
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+++ b/testsuite/synth/var01/tb_var04.vhdl
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+entity tb_var04 is
+end tb_var04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var04 is
+ signal clk : std_logic;
+ signal mask : std_logic_vector (1 downto 0);
+ signal val : std_logic_vector (15 downto 0);
+ signal res : std_logic_vector (15 downto 0);
+begin
+ dut: entity work.var04
+ port map (
+ mask => mask,
+ val => val,
+ res => res);
+
+ process
+ begin
+ mask <= "11";
+ val <= x"aa_bb";
+ wait for 1 ns;
+ assert res = x"aa_bb" severity failure;
+
+ mask <= "00";
+ val <= x"12_34";
+ wait for 1 ns;
+ assert res = x"00_00" severity failure;
+
+ mask <= "10";
+ val <= x"12_34";
+ wait for 1 ns;
+ assert res = x"12_00" severity failure;
+
+ wait;
+ end process;
+end behav;