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author | Tristan Gingold <tgingold@free.fr> | 2019-09-17 18:32:12 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-17 18:32:12 +0200 |
commit | eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107 (patch) | |
tree | d86fbc2d83d74dd1068daca870efd4f53b44432f /testsuite/synth/var01/tb_var06.vhdl | |
parent | 163a73a3501cb9f34025c3def6665cf161d744dc (diff) | |
download | ghdl-eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107.tar.gz ghdl-eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107.tar.bz2 ghdl-eb3d32a6de8822eb87a6bfd72dc1c94f9ff9a107.zip |
Add missing file for previous commit.
Diffstat (limited to 'testsuite/synth/var01/tb_var06.vhdl')
-rw-r--r-- | testsuite/synth/var01/tb_var06.vhdl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/var01/tb_var06.vhdl b/testsuite/synth/var01/tb_var06.vhdl new file mode 100644 index 000000000..492bcefb4 --- /dev/null +++ b/testsuite/synth/var01/tb_var06.vhdl @@ -0,0 +1,38 @@ +entity tb_var06 is +end tb_var06; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_var06 is + signal clk : std_logic; + signal mask : std_logic_vector (1 downto 0); + signal val : std_logic_vector (15 downto 0); + signal res : std_logic_vector (15 downto 0); +begin + dut: entity work.var06 + port map ( + mask => mask, + val => val, + res => res); + + process + begin + mask <= "11"; + val <= x"aa_bb"; + wait for 1 ns; + assert res = x"aa_bb" severity failure; + + mask <= "00"; + val <= x"12_34"; + wait for 1 ns; + assert res = x"00_00" severity failure; + + mask <= "10"; + val <= x"12_34"; + wait for 1 ns; + assert res = x"12_00" severity failure; + + wait; + end process; +end behav; |