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author | Tristan Gingold <tgingold@free.fr> | 2022-05-02 18:40:51 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-05-02 18:40:51 +0200 |
commit | 0abcd7c2c6a7e51c3c5e72f7ad6d05f1d4ae0e0a (patch) | |
tree | b0547011d9050caad544c049fa8526e16b329f5c /testsuite/synth | |
parent | fd518765a1f0d263d94a26f825d821c38ee1593a (diff) | |
download | ghdl-0abcd7c2c6a7e51c3c5e72f7ad6d05f1d4ae0e0a.tar.gz ghdl-0abcd7c2c6a7e51c3c5e72f7ad6d05f1d4ae0e0a.tar.bz2 ghdl-0abcd7c2c6a7e51c3c5e72f7ad6d05f1d4ae0e0a.zip |
testsuite/synth: add a test for #2049
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue2049/engine.vhdl | 96 | ||||
-rwxr-xr-x | testsuite/synth/issue2049/testsuite.sh | 7 |
2 files changed, 103 insertions, 0 deletions
diff --git a/testsuite/synth/issue2049/engine.vhdl b/testsuite/synth/issue2049/engine.vhdl new file mode 100644 index 000000000..2f016d90c --- /dev/null +++ b/testsuite/synth/issue2049/engine.vhdl @@ -0,0 +1,96 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity phony is + port ( + i : in std_logic; + o : out std_logic + ); +end entity; + +architecture synth of phony is + + constant BLOCKS : natural := 5000; + constant BITS : natural := 5; + + -- Unused but necessary to reproduce the crash : passing a vector is necessary + function func1(A : std_logic_vector) return natural is + begin + return 1; + end function; + + function func2(b : boolean) return natural is + begin + return func1(std_logic_vector(to_unsigned(0, BITS))); + end function; + + -- Unused but necessary to reproduce the crash + constant x : natural := func2(true); + + component LUT is + port ( + O : out std_logic; + I0 : in std_logic + ); + end component; + +begin + + gen : for b in 0 to BLOCKS-1 generate + + -- Both of these, lut and process, can reproduce the crash + + l : LUT + port map ( + O => open, + I0 => '0' + ); + + p : process(all) + variable v : natural; + begin + v := BITS; + end process; + + end generate; + + o <= i; + +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.all; + +entity engine is + generic ( + SIZE : natural := 10 + ); + port ( + i : in std_logic; + o : out std_logic + ); +end entity; + +architecture synth of engine is + +begin + + gen : for c in 0 to SIZE-1 generate + + ph : entity phony + port map ( + i => '0', + o => open + ); + + end generate; + + o <= i; + +end architecture; + diff --git a/testsuite/synth/issue2049/testsuite.sh b/testsuite/synth/issue2049/testsuite.sh new file mode 100755 index 000000000..992480f20 --- /dev/null +++ b/testsuite/synth/issue2049/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --std=08 engine.vhdl -e > syn_engine.vhdl + +echo "Test successful" |