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author | Tristan Gingold <tgingold@free.fr> | 2020-09-19 09:53:09 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-09-19 09:53:09 +0200 |
commit | 1337962c251723acaf021a8df2efbc261804f88a (patch) | |
tree | c0db2bfd47044a576f8cc519783275f9606e17c5 /testsuite/synth | |
parent | 2fb5d3fa8e642f5f268f106a99af771e2076c8d2 (diff) | |
download | ghdl-1337962c251723acaf021a8df2efbc261804f88a.tar.gz ghdl-1337962c251723acaf021a8df2efbc261804f88a.tar.bz2 ghdl-1337962c251723acaf021a8df2efbc261804f88a.zip |
testsuite/synth: add tests for find_leftmost/find_rightmost.
For #1460
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1460/division_float.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/issue1460/leftmost01.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/issue1460/leftmost02.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/issue1460/leftmost03.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/issue1460/rightmost01.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/issue1460/rightmost02.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/issue1460/tb_leftmost01.vhdl | 35 | ||||
-rw-r--r-- | testsuite/synth/issue1460/tb_leftmost02.vhdl | 25 | ||||
-rw-r--r-- | testsuite/synth/issue1460/tb_leftmost03.vhdl | 25 | ||||
-rw-r--r-- | testsuite/synth/issue1460/tb_rightmost01.vhdl | 35 | ||||
-rw-r--r-- | testsuite/synth/issue1460/tb_rightmost02.vhdl | 25 | ||||
-rwxr-xr-x | testsuite/synth/issue1460/testsuite.sh | 11 |
12 files changed, 241 insertions, 0 deletions
diff --git a/testsuite/synth/issue1460/division_float.vhdl b/testsuite/synth/issue1460/division_float.vhdl new file mode 100644 index 000000000..84c2951f9 --- /dev/null +++ b/testsuite/synth/issue1460/division_float.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.float_pkg.all; + +entity division_float is +port( +i0 : in float (7 downto -6); +i1 : in float (7 downto -6); +p0 : out float (7 downto -6)); +end division_float ; + +architecture arch1 of division_float is + +begin + p0 <= i0/i1 ; +end arch1; diff --git a/testsuite/synth/issue1460/leftmost01.vhdl b/testsuite/synth/issue1460/leftmost01.vhdl new file mode 100644 index 000000000..470ddfcca --- /dev/null +++ b/testsuite/synth/issue1460/leftmost01.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity leftmost01 is + port (d : unsigned (7 downto 0); + res : out integer); +end leftmost01; + +architecture behav of leftmost01 is +begin + res <= find_leftmost (d, '1'); +end behav; + diff --git a/testsuite/synth/issue1460/leftmost02.vhdl b/testsuite/synth/issue1460/leftmost02.vhdl new file mode 100644 index 000000000..019878072 --- /dev/null +++ b/testsuite/synth/issue1460/leftmost02.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity leftmost02 is + port (d : signed (8 to 12); + res : out integer); +end leftmost02; + +architecture behav of leftmost02 is +begin + res <= find_leftmost (d, '1'); +end behav; + diff --git a/testsuite/synth/issue1460/leftmost03.vhdl b/testsuite/synth/issue1460/leftmost03.vhdl new file mode 100644 index 000000000..c58d700b4 --- /dev/null +++ b/testsuite/synth/issue1460/leftmost03.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity leftmost03 is + port (d : unsigned (0 to 8); + res : out integer); +end leftmost03; + +architecture behav of leftmost03 is +begin + res <= find_leftmost (d, '1'); +end behav; + diff --git a/testsuite/synth/issue1460/rightmost01.vhdl b/testsuite/synth/issue1460/rightmost01.vhdl new file mode 100644 index 000000000..30ae1c64b --- /dev/null +++ b/testsuite/synth/issue1460/rightmost01.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rightmost01 is + port (d : unsigned (7 downto 0); + res : out integer); +end rightmost01; + +architecture behav of rightmost01 is +begin + res <= find_rightmost (d, '1'); +end behav; + diff --git a/testsuite/synth/issue1460/rightmost02.vhdl b/testsuite/synth/issue1460/rightmost02.vhdl new file mode 100644 index 000000000..a1d4724fe --- /dev/null +++ b/testsuite/synth/issue1460/rightmost02.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rightmost02 is + port (d : signed (2 to 4); + res : out integer); +end rightmost02; + +architecture behav of rightmost02 is +begin + res <= find_rightmost (d, '1'); +end behav; + diff --git a/testsuite/synth/issue1460/tb_leftmost01.vhdl b/testsuite/synth/issue1460/tb_leftmost01.vhdl new file mode 100644 index 000000000..669850b9a --- /dev/null +++ b/testsuite/synth/issue1460/tb_leftmost01.vhdl @@ -0,0 +1,35 @@ +entity tb_leftmost01 is +end tb_leftmost01; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_leftmost01 is + signal a : unsigned (7 downto 0); + signal b : unsigned (8 to 12); + signal c : unsigned (0 to 3); + signal ra, rb, rc : integer; +begin + dut_a: entity work.leftmost01 + port map (a, ra); +-- dut_b: entity work.leftmost01 +-- port map (b, rb); +-- dut_c: entity work.leftmost01 +-- port map (c, rc); + + process + begin + a <= b"0010_0101"; + b <= b"00101"; + c <= b"0000"; + + wait for 1 ns; + + assert ra = 5 severity failure; +-- assert rb = 10 severity failure; +-- assert rc = -1 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1460/tb_leftmost02.vhdl b/testsuite/synth/issue1460/tb_leftmost02.vhdl new file mode 100644 index 000000000..fbcb277ba --- /dev/null +++ b/testsuite/synth/issue1460/tb_leftmost02.vhdl @@ -0,0 +1,25 @@ +entity tb_leftmost02 is +end tb_leftmost02; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_leftmost02 is + signal b : signed (8 to 12); + signal rb : integer; +begin + dut_b: entity work.leftmost02 + port map (b, rb); + + process + begin + b <= b"00101"; + + wait for 1 ns; + + assert rb = 10 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1460/tb_leftmost03.vhdl b/testsuite/synth/issue1460/tb_leftmost03.vhdl new file mode 100644 index 000000000..132528ff9 --- /dev/null +++ b/testsuite/synth/issue1460/tb_leftmost03.vhdl @@ -0,0 +1,25 @@ +entity tb_leftmost03 is +end tb_leftmost03; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_leftmost03 is + signal c : unsigned (0 to 8); + signal rc : integer; +begin + dut_c: entity work.leftmost03 + port map (c, rc); + + process + begin + c <= b"0_0000_0000"; + + wait for 1 ns; + + assert rc = -1 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1460/tb_rightmost01.vhdl b/testsuite/synth/issue1460/tb_rightmost01.vhdl new file mode 100644 index 000000000..0196cfad0 --- /dev/null +++ b/testsuite/synth/issue1460/tb_rightmost01.vhdl @@ -0,0 +1,35 @@ +entity tb_rightmost01 is +end tb_rightmost01; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_rightmost01 is + signal a : unsigned (7 downto 0); + signal b : unsigned (8 to 12); + signal c : unsigned (0 to 3); + signal ra, rb, rc : integer; +begin + dut_a: entity work.rightmost01 + port map (a, ra); +-- dut_b: entity work.rightmost01 +-- port map (b, rb); +-- dut_c: entity work.rightmost01 +-- port map (c, rc); + + process + begin + a <= b"0010_0100"; + b <= b"00101"; + c <= b"0000"; + + wait for 1 ns; + + assert ra = 2 severity failure; +-- assert rb = 10 severity failure; +-- assert rc = -1 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1460/tb_rightmost02.vhdl b/testsuite/synth/issue1460/tb_rightmost02.vhdl new file mode 100644 index 000000000..cda7ae8f7 --- /dev/null +++ b/testsuite/synth/issue1460/tb_rightmost02.vhdl @@ -0,0 +1,25 @@ +entity tb_rightmost02 is +end tb_rightmost02; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_rightmost02 is + signal b : signed (2 to 4); + signal rb : integer; +begin + dut_b: entity work.rightmost02 + port map (b, rb); + + process + begin + b <= b"010"; + + wait for 1 ns; + + assert rb = 3 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1460/testsuite.sh b/testsuite/synth/issue1460/testsuite.sh new file mode 100755 index 000000000..b05373419 --- /dev/null +++ b/testsuite/synth/issue1460/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +for t in leftmost01 leftmost02 leftmost03 rightmost01 rightmost02; do + synth_tb $t +done + +echo "Test successful" |