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author | Tristan Gingold <tgingold@free.fr> | 2020-07-02 22:12:28 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-07-02 22:12:28 +0200 |
commit | 9828b5133870943106f78c734f0763829500e272 (patch) | |
tree | fd3cfd6801a0c1066c4065aa76d49281e993cbf3 /testsuite/synth | |
parent | 2c832dae31499fa8e8bd8d44d5f8abecae687f2e (diff) | |
download | ghdl-9828b5133870943106f78c734f0763829500e272.tar.gz ghdl-9828b5133870943106f78c734f0763829500e272.tar.bz2 ghdl-9828b5133870943106f78c734f0763829500e272.zip |
testsuite/synth: add tests for previous commits.
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1387/repro2.vhdl | 30 | ||||
-rwxr-xr-x | testsuite/synth/issue1387/testsuite.sh | 2 |
2 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/synth/issue1387/repro2.vhdl b/testsuite/synth/issue1387/repro2.vhdl new file mode 100644 index 000000000..3d1e33a8c --- /dev/null +++ b/testsuite/synth/issue1387/repro2.vhdl @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro2sub is + port (a,b : std_logic; + c : out std_logic; + p : inout std_logic); +end; + +architecture behav of repro2sub is +begin + c <= a xor b; +end behav; + +library ieee; +use ieee.std_logic_1164.all; + +entity repro2 is + port (a,b : std_logic; + c : out std_logic; + p : inout std_logic); +end; + +architecture behav of repro2 is + signal c1, c2 : std_logic; +begin + i1: entity work.repro2sub port map (a, b, c1, p); + i2: entity work.repro2sub port map (a, b, c2, p); + c <= c2 xor c1; +end behav; diff --git a/testsuite/synth/issue1387/testsuite.sh b/testsuite/synth/issue1387/testsuite.sh index c7cde0ee3..9174dc920 100755 --- a/testsuite/synth/issue1387/testsuite.sh +++ b/testsuite/synth/issue1387/testsuite.sh @@ -4,4 +4,6 @@ synth_failure repro1.vhdl -e +synth_analyze repro2 + echo "Test successful" |