testsuite/synth: add tests for std_logic_unsigned and std_logic_signed.

34 files changed, 1122 insertions, 0 deletions

diff --git a/testsuite/synth/snsuns01/sadds.vhdl b/testsuite/synth/snsuns01/sadds.vhdl
new file mode 100644
index 000000000..d8cf586a4
--- /dev/null
+++ b/testsuite/synth/snsuns01/sadds.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity adds is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    add_v4v3 : out std_logic_vector (3 downto 0);
+    add_v4i  : out std_logic_vector (3 downto 0);
+    add_iv3  : out std_logic_vector (2 downto 0);
+    add_v4l  : out std_logic_vector (3 downto 0);
+    add_lv3  : out std_logic_vector (2 downto 0));
+end adds;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of adds is
+begin
+  add_v4v3 <= l4 + r3;
+  add_v4i <= l4 + ri;
+  add_iv3 <= li + r3;
+  add_v4l <= l4 + r3(0);
+  add_lv3 <= l4(0) + r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/scmpeq.vhdl b/testsuite/synth/snsuns01/scmpeq.vhdl
new file mode 100644
index 000000000..d0ef55339
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmpeq.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpeq is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    eq_v4v3 : out boolean;
+    eq_v4i  : out boolean;
+    eq_iv3  : out boolean);
+end cmpeq;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmpeq is
+begin
+  eq_v4v3 <= l4 = r3;
+  eq_v4i  <= l4 = ri;
+  eq_iv3  <= li = r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/scmpge.vhdl b/testsuite/synth/snsuns01/scmpge.vhdl
new file mode 100644
index 000000000..3a4071210
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmpge.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpge is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    ge_v4v3 : out boolean;
+    ge_v4i  : out boolean;
+    ge_iv3  : out boolean);
+end cmpge;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmpge is
+begin
+  ge_v4v3 <= l4 >= r3;
+  ge_v4i  <= l4 >= ri;
+  ge_iv3  <= li >= r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/scmpgt.vhdl b/testsuite/synth/snsuns01/scmpgt.vhdl
new file mode 100644
index 000000000..e0b69cc2d
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmpgt.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpgt is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    gt_v4v3 : out boolean;
+    gt_v4i  : out boolean;
+    gt_iv3  : out boolean);
+end cmpgt;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmpgt is
+begin
+  gt_v4v3 <= l4 > r3;
+  gt_v4i  <= l4 > ri;
+  gt_iv3  <= li > r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/scmple.vhdl b/testsuite/synth/snsuns01/scmple.vhdl
new file mode 100644
index 000000000..a2d6f9538
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmple.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmple is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    le_v4v3 : out boolean;
+    le_v4i  : out boolean;
+    le_iv3  : out boolean);
+end cmple;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmple is
+begin
+  le_v4v3 <= l4 <= r3;
+  le_v4i  <= l4 <= ri;
+  le_iv3  <= li <= r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/scmplt.vhdl b/testsuite/synth/snsuns01/scmplt.vhdl
new file mode 100644
index 000000000..370b2a230
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmplt.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmplt is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    lt_v4v3 : out boolean;
+    lt_v4i  : out boolean;
+    lt_iv3  : out boolean);
+end cmplt;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmplt is
+begin
+  lt_v4v3 <= l4 < r3;
+  lt_v4i  <= l4 < ri;
+  lt_iv3  <= li < r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/scmpne.vhdl b/testsuite/synth/snsuns01/scmpne.vhdl
new file mode 100644
index 000000000..fdaae03ff
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmpne.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpne is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    ne_v4v3 : out boolean;
+    ne_v4i  : out boolean;
+    ne_iv3  : out boolean);
+end cmpne;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmpne is
+begin
+  ne_v4v3 <= l4 /= r3;
+  ne_v4i  <= l4 /= ri;
+  ne_iv3  <= li /= r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/smuls.vhdl b/testsuite/synth/snsuns01/smuls.vhdl
new file mode 100644
index 000000000..fb063368a
--- /dev/null
+++ b/testsuite/synth/snsuns01/smuls.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity muls is
+  port (
+    l3 : std_logic_vector (2 downto 0);
+    r4 : std_logic_vector (3 downto 0);
+
+    mul_v3v4 : out std_logic_vector (6 downto 0));
+end muls;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of muls is
+begin
+  mul_v3v4 <= l3 * r4;
+end behav;
diff --git a/testsuite/synth/snsuns01/sshrs.vhdl b/testsuite/synth/snsuns01/sshrs.vhdl
new file mode 100644
index 000000000..04bf1a5fb
--- /dev/null
+++ b/testsuite/synth/snsuns01/sshrs.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity shrs is
+  port (
+    l3 : std_logic_vector (2 downto 0);
+    r4 : std_logic_vector (3 downto 0);
+
+    shl_v3v4 : out std_logic_vector (2 downto 0);
+    shr_v3v4 : out std_logic_vector (2 downto 0));
+end shrs;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of shrs is
+begin
+  shl_v3v4 <= shl(l3, r4);
+  shr_v3v4 <= shr(l3, r4);
+end behav;
diff --git a/testsuite/synth/snsuns01/ssubs.vhdl b/testsuite/synth/snsuns01/ssubs.vhdl
new file mode 100644
index 000000000..ce3ab9f82
--- /dev/null
+++ b/testsuite/synth/snsuns01/ssubs.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity subs is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    sub_v4v3 : out std_logic_vector (3 downto 0);
+    sub_v4i  : out std_logic_vector (3 downto 0);
+    sub_iv3  : out std_logic_vector (2 downto 0);
+    sub_v4l  : out std_logic_vector (3 downto 0);
+    sub_lv3  : out std_logic_vector (2 downto 0));
+end subs;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of subs is
+begin
+  sub_v4v3 <= l4 - r3;
+  sub_v4i <= l4 - ri;
+  sub_iv3 <= li - r3;
+  sub_v4l <= l4 - r3(0);
+  sub_lv3 <= l4(0) - r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/sunaries.vhdl b/testsuite/synth/snsuns01/sunaries.vhdl
new file mode 100644
index 000000000..6df6a0063
--- /dev/null
+++ b/testsuite/synth/snsuns01/sunaries.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity unaries is
+  port (
+    l4 : std_logic_vector (3 downto 0);
+
+    plus_v    : out std_logic_vector (3 downto 0);
+    minus_v   : out std_logic_vector (3 downto 0);
+    abs_v     : out std_logic_vector (3 downto 0));
+end unaries;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of unaries is
+begin
+  plus_v  <= +l4;
+  minus_v <= -l4;
+  abs_v   <= abs l4;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_adds.vhdl b/testsuite/synth/snsuns01/tb_adds.vhdl
new file mode 100644
index 000000000..df8c4ed0a
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_adds.vhdl
@@ -0,0 +1,70 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_adds is
+end;
+
+architecture behav of tb_adds is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+
+  signal add_v4v3 : std_logic_vector (3 downto 0);
+  signal add_v4i  : std_logic_vector (3 downto 0);
+  signal add_iv3  : std_logic_vector (2 downto 0);
+  signal add_v4l  : std_logic_vector (3 downto 0);
+  signal add_lv3  : std_logic_vector (2 downto 0);
+begin
+
+  dut: entity work.adds
+    port map (
+      li       => li,
+      ri       => ri,
+      l4       => l4,
+      r3       => r3,
+      add_v4v3 => add_v4v3,
+      add_v4i  => add_v4i,
+      add_iv3  => add_iv3,
+      add_v4l  => add_v4l,
+      add_lv3  => add_lv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & to_string(l4) & " + " & to_string(r3) & " = "
+          & to_string(add_v4v3);
+        report "v4i:  " & to_string(l4) & " + " & integer'image(j) & " = "
+          & to_string(add_v4i);
+        report "iv3:  " & integer'image(i) & " + " & to_string(r3) & " = "
+          & to_string(add_iv3);
+        report "v4l:  " & to_string(l4) & " + " & sl_map(r3(0)) & " = "
+          & to_string(add_v4l);
+        report "lv3:  " & sl_map (l4(0)) & " + " & to_string(r3) & " = "
+          & to_string(add_lv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_cmpeq.vhdl b/testsuite/synth/snsuns01/tb_cmpeq.vhdl
new file mode 100644
index 000000000..ba0ac5c4d
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_cmpeq.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpeq is
+end;
+
+architecture behav of tb_cmpeq is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal eq_v4v3 : boolean;
+  signal eq_v4i :  boolean;
+  signal eq_iv3 :  boolean;
+begin
+
+  dut: entity work.cmpeq
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      eq_v4v3 => eq_v4v3,
+      eq_v4i  => eq_v4i,
+      eq_iv3  => eq_iv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(eq_v4v3);
+        report "v4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(eq_v4i);
+        report "iv3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(eq_iv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_cmpge.vhdl b/testsuite/synth/snsuns01/tb_cmpge.vhdl
new file mode 100644
index 000000000..536a0a247
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_cmpge.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpge is
+end;
+
+architecture behav of tb_cmpge is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal ge_v4v3 : boolean;
+  signal ge_v4i :  boolean;
+  signal ge_iv3 :  boolean;
+begin
+
+  dut: entity work.cmpge
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      ge_v4v3 => ge_v4v3,
+      ge_v4i  => ge_v4i,
+      ge_iv3  => ge_iv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(ge_v4v3);
+        report "v4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(ge_v4i);
+        report "iv3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(ge_iv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_cmpgt.vhdl b/testsuite/synth/snsuns01/tb_cmpgt.vhdl
new file mode 100644
index 000000000..8b10e6b23
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_cmpgt.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpgt is
+end;
+
+architecture behav of tb_cmpgt is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal gt_v4v3 : boolean;
+  signal gt_v4i :  boolean;
+  signal gt_iv3 :  boolean;
+begin
+
+  dut: entity work.cmpgt
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      gt_v4v3 => gt_v4v3,
+      gt_v4i  => gt_v4i,
+      gt_iv3  => gt_iv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(gt_v4v3);
+        report "v4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(gt_v4i);
+        report "iv3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(gt_iv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_cmple.vhdl b/testsuite/synth/snsuns01/tb_cmple.vhdl
new file mode 100644
index 000000000..1a0f216aa
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_cmple.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmple is
+end;
+
+architecture behav of tb_cmple is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal le_v4v3 : boolean;
+  signal le_v4i :  boolean;
+  signal le_iv3 :  boolean;
+begin
+
+  dut: entity work.cmple
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      le_v4v3 => le_v4v3,
+      le_v4i  => le_v4i,
+      le_iv3  => le_iv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(le_v4v3);
+        report "v4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(le_v4i);
+        report "iv3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(le_iv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_cmplt.vhdl b/testsuite/synth/snsuns01/tb_cmplt.vhdl
new file mode 100644
index 000000000..2fe7e0219
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_cmplt.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmplt is
+end;
+
+architecture behav of tb_cmplt is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal lt_v4v3 : boolean;
+  signal lt_v4i :  boolean;
+  signal lt_iv3 :  boolean;
+begin
+
+  dut: entity work.cmplt
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      lt_v4v3 => lt_v4v3,
+      lt_v4i  => lt_v4i,
+      lt_iv3  => lt_iv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_v4v3);
+        report "v4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_v4i);
+        report "iv3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_iv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_cmpne.vhdl b/testsuite/synth/snsuns01/tb_cmpne.vhdl
new file mode 100644
index 000000000..b97e9ddd5
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_cmpne.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpne is
+end;
+
+architecture behav of tb_cmpne is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal ne_v4v3 : boolean;
+  signal ne_v4i :  boolean;
+  signal ne_iv3 :  boolean;
+begin
+
+  dut: entity work.cmpne
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      ne_v4v3 => ne_v4v3,
+      ne_v4i  => ne_v4i,
+      ne_iv3  => ne_iv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(ne_v4v3);
+        report "v4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(ne_v4i);
+        report "iv3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(ne_iv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_muls.vhdl b/testsuite/synth/snsuns01/tb_muls.vhdl
new file mode 100644
index 000000000..f96a0b0f1
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_muls.vhdl
@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_muls is
+end;
+
+architecture behav of tb_muls is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer := 0;
+  signal ri : integer := 0;
+
+  signal l3       : std_logic_vector (2 downto 0) := "000";
+  signal r4       : std_logic_vector (3 downto 0) := "0000";
+  signal mul_v3v4 : std_logic_vector (6 downto 0);
+begin
+
+  dut: entity work.muls
+    port map (
+      l3        => l3,
+      r4        => r4,
+      mul_v3v4 => mul_v3v4);
+
+  process
+  begin
+    for i in -4 to 3 loop
+      li <= i;
+      l3 <= conv_std_logic_vector (i, 3);
+      for j in 0 to 5 loop
+        r4 <= conv_std_logic_vector (j, 4);
+        ri <= j;
+        wait for 1 ns;
+        report "v3v4: " & integer'image(i) & " mul " & integer'image(j) & " = "
+          & to_string(mul_v3v4);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_shrs.vhdl b/testsuite/synth/snsuns01/tb_shrs.vhdl
new file mode 100644
index 000000000..2e0343350
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_shrs.vhdl
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_shrs is
+end;
+
+architecture behav of tb_shrs is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer := 0;
+  signal ri : integer := 0;
+
+  signal l3       : std_logic_vector (2 downto 0) := "000";
+  signal r4       : std_logic_vector (3 downto 0) := "0000";
+  signal shl_v3v4 : std_logic_vector (2 downto 0);
+  signal shr_v3v4 : std_logic_vector (2 downto 0);
+begin
+
+  dut: entity work.shrs
+    port map (
+      l3        => l3,
+      r4        => r4,
+      shl_v3v4 => shl_v3v4,
+      shr_v3v4 => shr_v3v4);
+
+  process
+  begin
+    for i in -4 to 3 loop
+      li <= i;
+      l3 <= conv_std_logic_vector (i, 3);
+      for j in 0 to 5 loop
+        r4 <= conv_std_logic_vector (j, 4);
+        ri <= j;
+        wait for 1 ns;
+        report "v3v4: " & integer'image(i) & " shl " & integer'image(j) & " = "
+          & to_string(shl_v3v4);
+        report "v3v4: " & integer'image(i) & " shr " & integer'image(j) & " = "
+          & to_string(shr_v3v4);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_subs.vhdl b/testsuite/synth/snsuns01/tb_subs.vhdl
new file mode 100644
index 000000000..95a9fea99
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_subs.vhdl
@@ -0,0 +1,70 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_subs is
+end;
+
+architecture behav of tb_subs is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+
+  signal sub_v4v3 : std_logic_vector (3 downto 0);
+  signal sub_v4i  : std_logic_vector (3 downto 0);
+  signal sub_iv3  : std_logic_vector (2 downto 0);
+  signal sub_v4l  : std_logic_vector (3 downto 0);
+  signal sub_lv3  : std_logic_vector (2 downto 0);
+begin
+
+  dut: entity work.subs
+    port map (
+      li       => li,
+      ri       => ri,
+      l4       => l4,
+      r3       => r3,
+      sub_v4v3 => sub_v4v3,
+      sub_v4i  => sub_v4i,
+      sub_iv3  => sub_iv3,
+      sub_v4l  => sub_v4l,
+      sub_lv3  => sub_lv3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "v4v3: " & to_string(l4) & " - " & to_string(r3) & " = "
+          & to_string(sub_v4v3);
+        report "v4i:  " & to_string(l4) & " - " & integer'image(j) & " = "
+          & to_string(sub_v4i);
+        report "iv3:  " & integer'image(i) & " - " & to_string(r3) & " = "
+          & to_string(sub_iv3);
+        report "v4l:  " & to_string(l4) & " - " & sl_map(r3(0)) & " = "
+          & to_string(sub_v4l);
+        report "lv3:  " & sl_map (l4(0)) & " - " & to_string(r3) & " = "
+          & to_string(sub_lv3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/tb_unaries.vhdl b/testsuite/synth/snsuns01/tb_unaries.vhdl
new file mode 100644
index 000000000..66fc8e9cc
--- /dev/null
+++ b/testsuite/synth/snsuns01/tb_unaries.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_unaries is
+end;
+
+architecture behav of tb_unaries is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer;
+  signal l4        : std_logic_vector (3 downto 0);
+  signal plus_v  : std_logic_vector (3 downto 0);
+  signal minus_v  : std_logic_vector (3 downto 0);
+  signal abs_v  : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.unaries
+    port map (
+      l4        => l4,
+      plus_v  => plus_v,
+      minus_v => minus_v,
+      abs_v   => abs_v);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      wait for 1 ns;
+      report "v4: + " & integer'image(i) & " = " & to_string(plus_v);
+      report "v4: - " & integer'image(i) & " = " & to_string(minus_v);
+      report "v4: abs " & integer'image(i) & " = " & to_string(abs_v);
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/snsuns01/testsuite.sh b/testsuite/synth/snsuns01/testsuite.sh
new file mode 100755
index 000000000..453469303
--- /dev/null
+++ b/testsuite/synth/snsuns01/testsuite.sh
@@ -0,0 +1,25 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS="-fsynopsys -fexplicit"
+
+# Compare opers.
+for s in u s; do
+    for f in adds subs unaries muls cmplt cmple cmpgt cmpge cmpeq cmpne shrs; do
+        analyze $s$f.vhdl
+        analyze tb_$f.vhdl
+        elab_simulate tb_$f > $s$f.ref
+
+        synth $s$f.vhdl -e > syn_$s$f.vhdl
+        analyze tb_$f.vhdl
+        elab_simulate tb_$f > $s$f.out
+
+        diff --strip-trailing-cr $s$f.out $s$f.ref
+    done
+
+  clean
+done
+
+
+echo "Test successful"
diff --git a/testsuite/synth/snsuns01/uadds.vhdl b/testsuite/synth/snsuns01/uadds.vhdl
new file mode 100644
index 000000000..060c5cfc6
--- /dev/null
+++ b/testsuite/synth/snsuns01/uadds.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity adds is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    add_v4v3 : out std_logic_vector (3 downto 0);
+    add_v4i  : out std_logic_vector (3 downto 0);
+    add_iv3  : out std_logic_vector (2 downto 0);
+    add_v4l  : out std_logic_vector (3 downto 0);
+    add_lv3  : out std_logic_vector (2 downto 0));
+end adds;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of adds is
+begin
+  add_v4v3 <= l4 + r3;
+  add_v4i <= l4 + ri;
+  add_iv3 <= li + r3;
+  add_v4l <= l4 + r3(0);
+  add_lv3 <= l4(0) + r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/ucmpeq.vhdl b/testsuite/synth/snsuns01/ucmpeq.vhdl
new file mode 100644
index 000000000..f6a889edc
--- /dev/null
+++ b/testsuite/synth/snsuns01/ucmpeq.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpeq is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    eq_v4v3 : out boolean;
+    eq_v4i  : out boolean;
+    eq_iv3  : out boolean);
+end cmpeq;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of cmpeq is
+begin
+  eq_v4v3 <= l4 = r3;
+  eq_v4i  <= l4 = ri;
+  eq_iv3  <= li = r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/ucmpge.vhdl b/testsuite/synth/snsuns01/ucmpge.vhdl
new file mode 100644
index 000000000..9b2a75e51
--- /dev/null
+++ b/testsuite/synth/snsuns01/ucmpge.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpge is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    ge_v4v3 : out boolean;
+    ge_v4i  : out boolean;
+    ge_iv3  : out boolean);
+end cmpge;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of cmpge is
+begin
+  ge_v4v3 <= l4 >= r3;
+  ge_v4i  <= l4 >= ri;
+  ge_iv3  <= li >= r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/ucmpgt.vhdl b/testsuite/synth/snsuns01/ucmpgt.vhdl
new file mode 100644
index 000000000..7193c5f69
--- /dev/null
+++ b/testsuite/synth/snsuns01/ucmpgt.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpgt is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    gt_v4v3 : out boolean;
+    gt_v4i  : out boolean;
+    gt_iv3  : out boolean);
+end cmpgt;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of cmpgt is
+begin
+  gt_v4v3 <= l4 > r3;
+  gt_v4i  <= l4 > ri;
+  gt_iv3  <= li > r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/ucmple.vhdl b/testsuite/synth/snsuns01/ucmple.vhdl
new file mode 100644
index 000000000..2f39e205d
--- /dev/null
+++ b/testsuite/synth/snsuns01/ucmple.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmple is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    le_v4v3 : out boolean;
+    le_v4i  : out boolean;
+    le_iv3  : out boolean);
+end cmple;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of cmple is
+begin
+  le_v4v3 <= l4 <= r3;
+  le_v4i  <= l4 <= ri;
+  le_iv3  <= li <= r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/ucmplt.vhdl b/testsuite/synth/snsuns01/ucmplt.vhdl
new file mode 100644
index 000000000..aa2f19bb3
--- /dev/null
+++ b/testsuite/synth/snsuns01/ucmplt.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmplt is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    lt_v4v3 : out boolean;
+    lt_v4i  : out boolean;
+    lt_iv3  : out boolean);
+end cmplt;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of cmplt is
+begin
+  lt_v4v3 <= l4 < r3;
+  lt_v4i  <= l4 < ri;
+  lt_iv3  <= li < r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/ucmpne.vhdl b/testsuite/synth/snsuns01/ucmpne.vhdl
new file mode 100644
index 000000000..346b86b6b
--- /dev/null
+++ b/testsuite/synth/snsuns01/ucmpne.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpne is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    ne_v4v3 : out boolean;
+    ne_v4i  : out boolean;
+    ne_iv3  : out boolean);
+end cmpne;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of cmpne is
+begin
+  ne_v4v3 <= l4 /= r3;
+  ne_v4i  <= l4 /= ri;
+  ne_iv3  <= li /= r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/umuls.vhdl b/testsuite/synth/snsuns01/umuls.vhdl
new file mode 100644
index 000000000..57971d214
--- /dev/null
+++ b/testsuite/synth/snsuns01/umuls.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity muls is
+  port (
+    l3 : std_logic_vector (2 downto 0);
+    r4 : std_logic_vector (3 downto 0);
+
+    mul_v3v4 : out std_logic_vector (6 downto 0));
+end muls;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of muls is
+begin
+  mul_v3v4 <= l3 * r4;
+end behav;
diff --git a/testsuite/synth/snsuns01/ushrs.vhdl b/testsuite/synth/snsuns01/ushrs.vhdl
new file mode 100644
index 000000000..f3539fe62
--- /dev/null
+++ b/testsuite/synth/snsuns01/ushrs.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity shrs is
+  port (
+    l3 : std_logic_vector (2 downto 0);
+    r4 : std_logic_vector (3 downto 0);
+
+    shl_v3v4 : out std_logic_vector (2 downto 0);
+    shr_v3v4 : out std_logic_vector (2 downto 0));
+end shrs;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of shrs is
+begin
+  shl_v3v4 <= shl(l3, r4);
+  shr_v3v4 <= shr(l3, r4);
+end behav;
diff --git a/testsuite/synth/snsuns01/usubs.vhdl b/testsuite/synth/snsuns01/usubs.vhdl
new file mode 100644
index 000000000..d77decff0
--- /dev/null
+++ b/testsuite/synth/snsuns01/usubs.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity subs is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    sub_v4v3 : out std_logic_vector (3 downto 0);
+    sub_v4i  : out std_logic_vector (3 downto 0);
+    sub_iv3  : out std_logic_vector (2 downto 0);
+    sub_v4l  : out std_logic_vector (3 downto 0);
+    sub_lv3  : out std_logic_vector (2 downto 0));
+end subs;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of subs is
+begin
+  sub_v4v3 <= l4 - r3;
+  sub_v4i <= l4 - ri;
+  sub_iv3 <= li - r3;
+  sub_v4l <= l4 - r3(0);
+  sub_lv3 <= l4(0) - r3;
+end behav;
diff --git a/testsuite/synth/snsuns01/uunaries.vhdl b/testsuite/synth/snsuns01/uunaries.vhdl
new file mode 100644
index 000000000..568dec09d
--- /dev/null
+++ b/testsuite/synth/snsuns01/uunaries.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity unaries is
+  port (
+    l4 : std_logic_vector (3 downto 0);
+
+    plus_v    : out std_logic_vector (3 downto 0);
+    minus_v   : out std_logic_vector (3 downto 0);
+    abs_v     : out std_logic_vector (3 downto 0));
+end unaries;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture behav of unaries is
+begin
+  plus_v  <= +l4;
+  --  Dummy for compatibility with signed operations.
+  minus_v <= not l4;
+  abs_v   <= +l4;
+end behav;