Import vests testsuite

5 files changed, 518 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams
new file mode 100644
index 000000000..1c9b85e58
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test107.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test107.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correct impelmentation of the port terminal
+-- decl. signal decl. of type real, type array decl. 
+-- the test performs a 4 bit digital to analog conversion.
+----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+  NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+END electricalsystem;
+
+USE work.electricalsystem.all;
+ENTITY dac is
+  port(inputvector : in bit_vector(3 downto 0); --inputvector is an array of 16 bits
+       terminal T1, T2: electrical);	--terminal declarations
+END dac;
+
+ARCHITECTURE behavior OF dac IS
+
+  type temp_array is array(0 to 3) of integer; -- temp to store the array values
+  quantity vout across T1 to T2;	--output of the dac
+  
+  signal vout_sig, vcopy : real;	
+BEGIN
+
+  dac_process: PROCESS(inputvector) 
+    variable a : temp_array := (0,0,0,0);
+    variable tmp : real;
+    
+  BEGIN
+    for index in 3 downto 0 loop
+      if inputvector(index) = '0' then
+	a(index) := 0;			--bit to integer conversion done here
+      else a(index) := 1; 
+      end if;
+    end loop;
+
+    tmp := real(a(3)*8) + real(a(2)*4) + real(a(1)*2 + a(0)); --find the corresponding value of the binary 
+    vout_sig <= tmp;		
+
+  END PROCESS dac_process;
+
+  -- digital to analog conversion is done here
+  vout == vcopy;
+
+  convert: process(vout_sig)
+  begin
+    vcopy <= TRANSPORT vout_sig;
+  end process;
+
+END behavior;
+use work.electricalsystem.all;
+ENTITY tb_dac is
+end tb_dac;
+
+architecture stimuli of tb_dac is
+  signal myinputvector : bit_vector(3 downto 0);
+  terminal tout : electrical;
+  component dac port( inputvector : in bit_vector(3 downto 0);
+                      terminal T1, T2: electrical);
+  end component;
+  for all: dac use entity work.dac(behavior);
+  
+BEGIN
+  
+  unit:dac port map (myinputvector, tout, electrical'reference);
+
+  stimuli_process: process
+  BEGIN
+    
+    myinputvector <= "0000";
+    wait for 10 ns;
+
+   myinputvector <= "0001";
+    wait for 10 ns;
+
+  myinputvector <= "0010";
+    wait for 10 ns;
+
+    myinputvector <= "0100";
+    wait for 10 ns;
+
+    myinputvector <= "1000";
+    wait for 10 ns;
+
+    myinputvector <= "1100";
+    wait for 10 ns;
+
+    myinputvector <= "1110";    
+    wait for 10 ns;
+
+    myinputvector <= "1101"; 
+    wait for 10 ns;
+
+    myinputvector <= "1111"; 
+    wait for 10 ns;
+    myinputvector <= "0000";
+    wait for 10 ns;
+  
+    myinputvector <= "1100";
+    wait for 10 ns;
+    
+    myinputvector <= "1010";
+    wait for 10 ns;
+  
+    wait;
+  end process;
+end stimuli;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams
new file mode 100644
index 000000000..d59b2de7e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test129.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+     NATURE electrical IS real ACROSS real THROUGH ground reference; 
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    nature electrical_vector is array(natural range<>) of electrical;
+    subnature el_vec is electrical_vector(0 to 3);
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+generic( a: real);
+port( terminal ip: el_vec;
+      terminal op:electrical);
+end entity;
+
+architecture atest of test is
+variable a:real:=5.0;
+variable output:real:=0.0;
+quantity vin across ip ;
+quantity vout across iout through ip to op;
+begin
+
+   for i in 0 to 3 loop
+	output:=output + vin(i)*a;
+   end loop;
+vout:=output;
+
+end architecture atest;
+
+use work.electricalSystem.all;
+entity tb is
+end entity;
+
+architecture atb of tb is
+quantity  myvector : el_vec(0 to 3);
+terminal top:electrical;
+component test 
+	port(terminal ip, op: electrical);
+end component;
+for all: test use entity work.test(atest);
+begin
+
+unit: test port map(tip, top, ground);
+
+a_process: process
+begin
+
+myvector == 1.0;
+wait for 10 ns;
+myvector  == 2.0;
+wait for 10 ns;
+myvector  == 2.0;
+wait for 10 ns;
+myvector  ==1.0;
+wait for 10 ns;
+
+wait;
+
+end process;
+
+end atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams
new file mode 100644
index 000000000..c92b11b4a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test130.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH ground reference; 
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    nature electrical_vector is array(natural range<>) of electrical;
+    subnature el_vec is electrical_vector(0 to 3);
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+generic( a: real);
+port( terminal ip: el_vec;
+      terminal op:electrical);
+end entity;
+
+architecture atest of test is
+variable a:real:=5.0;
+variable output:real:=0.0;
+quantity vin0 across ip(0) to op;
+quantity vin1 across ip(1) to op;
+quantity vin2 across ip(2) to op;
+quantity vin3 across ip(3) to op;
+quantity vout across iout through op;
+
+begin
+
+e1: vin0 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+e2: vin1 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+e3: vin2 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+e4: vin3 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+
+vout == (vin0+vin1+vin2+vin3)*a;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams
new file mode 100644
index 000000000..8d813451c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test139.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+-----------------------------------------------------------------------
+-- File          : test139.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+-----------------------------------------------------------------------
+-- Description :
+-----------------------------------------------------------------------
+-- this test checks the correctness of the record declaration as a type
+-- it also checks for the usage of the record element declarations.
+-- the assert statement is also checked.
+-- the record is declared within a package
+-- the test also checks the correctness of the function impelmentation.
+-- the function accepts the record parameters and returns the result of 
+-- type real.
+-----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+ 
+    SUBTYPE voltage IS real;
+    SUBTYPE current IS real;
+ 
+    NATURE electrical IS
+        voltage ACROSS
+        current THROUGH ground reference;
+ 
+END PACKAGE electricalsystem;
+ 
+PACKAGE types IS
+ 
+    TYPE cmodel IS RECORD
+        cj     : real;    
+        cjsw   : real;    
+        defw   : real;    
+        narrow : real;    
+    END RECORD;
+ 
+END PACKAGE types;
+ 
+USE work.electricalsystem.all;
+USE work.types.all;
+ 
+ENTITY test IS
+    GENERIC (cnom : real := 0.0;
+             model : cmodel := (0.0, 0.0, 1.0e-6, 0.0);
+             l : real := 0.0;
+             w : real := 0.0;
+             ic : real := 0.0 );
+    PORT (TERMINAL t1,t2 : electrical);
+END ENTITY test;
+ 
+ARCHITECTURE atest OF test IS
+    	FUNCTION c_init (	cnom : real;
+             		model : cmodel;
+             		l, w : real)
+        RETURN real IS
+        VARIABLE ceff : real;  -- effective capacitance value
+        VARIABLE weff : real;  -- effective channel width
+ 	BEGIN
+ 
+        IF cnom /= 0.0 THEN
+            ASSERT (model.cj = 0.0 AND model.cjsw = 0.0)
+                    REPORT "Both cnom and model specified";
+            ceff := cnom;
+        ELSE
+            ASSERT (l > 0.0)
+                    REPORT "Channel length not specified";
+            IF w = 0.0 THEN
+                weff := model.defw;
+            ELSE
+                weff := w;
+            END IF;
+            ASSERT (weff > 0.0) 
+                    REPORT "Channel width not specified";
+            ceff := model.cj*(l-model.narrow)*(weff-model.narrow) +
+                        model.cjsw*(l+weff-2.0*model.narrow);
+        END IF;
+        RETURN (ceff);
+    	END FUNCTION c_init;
+ 
+    	CONSTANT ceff : real := c_init(cnom, model, l, w);
+    	QUANTITY v ACROSS i THROUGH t1 TO t2;
+BEGIN
+    i == ceff * v'dot;
+END ARCHITECTURE atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams
new file mode 100644
index 000000000..fd22b2a7d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test186.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    subtype voltage is real ;
+    subtype current is real ;
+
+   NATURE electrical IS voltage ACROSS current THROUGH Ground reference;
+   --NATURE electrical IS real ACROSS real THROUGH Ground reference;
+   NATURE electrical_vector is array(natural range<>) of electrical ;
+   --type real_vector is array(natural range<>) of voltage ;
+   subnature el_vec is electrical_vector(0 to 100);
+   FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+  
+--entity declaration
+
+ENTITY RLC IS
+   
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+    
+   terminal n1 : electrical; 
+   terminal n2: el_vec;
+   
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to ground;
+   quantity vs across n1 ;
+   constant r1 : REAL := 20.0;
+   constant r2 : REAL := 10.0;
+
+
+BEGIN
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                              * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;