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author | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams')
-rw-r--r-- | testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams new file mode 100644 index 000000000..bb2cf7d52 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tick_left.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +-- A simple RC circuit but both R & C are in between array terminals. +-- trying to use 'left, 'right, 'low, 'high attributes. + +PACKAGE electricalSystem IS + subtype voltage is real ; + subtype current is real ; + + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + NATURE electrical_vector is array(natural range<>) of electrical ; + subnature el_vect4 is electrical_vector(1 to 2); + + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1: electrical; + terminal n2: el_vect4; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 to Ground; + quantity vs across n1 ; + constant r1 : REAL := 1000.0; + constant cap : REAL := 100.0e-9; + +BEGIN + +res11 : vr1(n2'left) == ir1(n2'left) * r1; +res12 : vr1(el_vect4'right) == ir1(el_vect4'right) * r1; +cap11 : ir2(el_vect4'low) == vr2(1)'dot * cap; +cap12 : ir2(el_vect4'high) == cap * vr2(2)'dot; + +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 15.0 --sine source + * real(time'pos(now)) * 1.0e-13); + +END architecture behavior; |