Import vests testsuite

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diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd
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+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity and_multiple is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_multiple;
+
+--------------------------------------------------
+
+architecture behavioral of and_multiple is
+begin
+
+  and_reducer : process ( i ) is
+    variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result;
+  end process and_reducer;
+
+end architecture behavioral;