aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2021-08-31 04:56:32 +0200
committerTristan Gingold <tgingold@free.fr>2021-08-31 04:56:32 +0200
commit0129b31a35070a719b2e616b83eadff06c284d12 (patch)
tree12b3211cdd86a60cea3a99f84eae2804a22d6674 /testsuite
parent631beae9b98755b5cb59f779b1fa7a78e113e3ca (diff)
downloadghdl-0129b31a35070a719b2e616b83eadff06c284d12.tar.gz
ghdl-0129b31a35070a719b2e616b83eadff06c284d12.tar.bz2
ghdl-0129b31a35070a719b2e616b83eadff06c284d12.zip
testsuite/synth: add a test for #1654
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue1654/checker.vhdl25
-rw-r--r--testsuite/synth/issue1654/tb_checker.vhdl86
-rwxr-xr-xtestsuite/synth/issue1654/testsuite.sh21
3 files changed, 132 insertions, 0 deletions
diff --git a/testsuite/synth/issue1654/checker.vhdl b/testsuite/synth/issue1654/checker.vhdl
new file mode 100644
index 000000000..0f302fe5b
--- /dev/null
+++ b/testsuite/synth/issue1654/checker.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity checker is
+ port (
+ clk : in std_logic;
+ a, b, c, d : std_logic
+ );
+end;
+
+
+architecture psl of checker is
+begin
+ -- All is sensitive to rising edge of clk
+ default clock is rising_edge(clk);
+
+ -- This assertion holds
+ WITH_sync_ABORT_a : assert (always a -> next (b before a)) sync_abort c;
+
+ -- This assertion should also hold, but it does not
+ -- GHDL seems to implement abort as sync_abort instead of async_abort
+ -- See 1850-2010 6.2.1.5.1 abort, async_abort, and sync_abort
+ WITH_async_ABORT_a : assert (always a -> next (b before a)) async_abort d;
+end architecture psl;
+
diff --git a/testsuite/synth/issue1654/tb_checker.vhdl b/testsuite/synth/issue1654/tb_checker.vhdl
new file mode 100644
index 000000000..f52e7ae8e
--- /dev/null
+++ b/testsuite/synth/issue1654/tb_checker.vhdl
@@ -0,0 +1,86 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+
+entity sequencer is
+ generic (
+ seq : string
+ );
+ port (
+ clk : in std_logic;
+ data : out std_logic
+ );
+end entity sequencer;
+
+
+architecture rtl of sequencer is
+
+ signal index : natural := seq'low;
+
+ function to_bit (a : in character) return std_logic is
+ variable ret : std_logic;
+ begin
+ case a is
+ when '0' | '_' => ret := '0';
+ when '1' | '-' => ret := '1';
+ when others => ret := 'X';
+ end case;
+ return ret;
+ end function to_bit;
+
+begin
+
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if (index < seq'high) then
+ index <= index + 1;
+ end if;
+ end if;
+ end process;
+
+ data <= to_bit(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+use std.env.all;
+
+entity tb_checker is
+end;
+
+architecture sim of tb_checker is
+ signal clk : std_logic := '1';
+ signal a, b, c, d : std_logic;
+begin
+ clk <= not clk after 500 ps;
+
+ -- async reset 100 ps after rising edge in cycle 1
+ d <= '0', '1' after 1100 ps, '0' after 1400 ps;
+
+ -- 0123456789
+ SEQ_A : entity work.sequencer generic map ("-___-_____") port map (clk, a);
+ SEQ_B : entity work.sequencer generic map ("_______-__") port map (clk, b);
+ SEQ_C : entity work.sequencer generic map ("-_________") port map (clk, c);
+ -- D : _|________
+
+ dut: entity work.checker port map
+ (clk => clk, a => a, b => b, c => c, d => d);
+
+ -- stop simulation after 10 cycles
+ process
+ variable index : natural := 10;
+ begin
+ loop
+ wait until rising_edge(clk);
+ index := index - 1;
+ exit when index = 0;
+ end loop;
+ stop(0);
+ end process;
+
+
+end architecture sim;
diff --git a/testsuite/synth/issue1654/testsuite.sh b/testsuite/synth/issue1654/testsuite.sh
new file mode 100755
index 000000000..bfd1077f7
--- /dev/null
+++ b/testsuite/synth/issue1654/testsuite.sh
@@ -0,0 +1,21 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+# Need to disable asserts at 0.
+#synth_tb checker
+
+t=checker
+
+analyze $t.vhdl tb_$t.vhdl
+elab_simulate tb_$t
+clean
+
+synth $t.vhdl -e $t > syn_$t.vhdl
+analyze syn_$t.vhdl tb_$t.vhdl
+elab_simulate tb_$t --asserts=disable-at-0 --assert-level=error
+clean
+
+echo "Test successful"