testsuite/synth: add a test for #1658

4 files changed, 125 insertions, 0 deletions

diff --git a/testsuite/synth/issue1658/issue.vhdl b/testsuite/synth/issue1658/issue.vhdl
new file mode 100644
index 000000000..a27d2f352
--- /dev/null
+++ b/testsuite/synth/issue1658/issue.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+architecture psl of issue is
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+begin
+  -- Error occurs when using a generate statement
+  testG : if true generate
+
+    attribute anyconst : boolean;
+    signal b : natural;
+    attribute anyconst of b : signal is true;
+
+  begin
+
+    -- don't work
+    GEN_ASSUME : assume always b = 23;
+    GEN_ASSERT : assert always b = 23;
+
+  end generate testG;
+
+end architecture;
diff --git a/testsuite/synth/issue1658/issue_1658.vhdl b/testsuite/synth/issue1658/issue_1658.vhdl
new file mode 100644
index 000000000..53b68881a
--- /dev/null
+++ b/testsuite/synth/issue1658/issue_1658.vhdl
@@ -0,0 +1,57 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+
+architecture psl of issue is
+
+  attribute anyconst : boolean;
+  
+  signal a: natural;
+  attribute anyconst of a : signal is true;
+
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- works
+  assume always a = 42;
+  assert always a = 42;
+
+  -- Error occurs when using a generate statement
+  testG : if true generate
+
+    signal b : natural;
+    attribute anyconst of b : signal is true;
+
+  begin
+
+    -- works
+    GEN_ASSUME : assume always b = 23;
+    GEN_ASSERT : assert always b = 23;
+
+  end generate testG;
+
+  -- Same error occurs when using a block statement
+  testB : block is
+
+    signal c : natural;
+    attribute anyconst of c : signal is true;
+
+  begin
+
+    -- works
+    BLK_ASSUME : assume always c = 11;
+    BLK_ASSERT : assert always c = 11;
+
+  end block testB;
+
+
+end architecture psl;
diff --git a/testsuite/synth/issue1658/ok.vhdl b/testsuite/synth/issue1658/ok.vhdl
new file mode 100644
index 000000000..d8649301a
--- /dev/null
+++ b/testsuite/synth/issue1658/ok.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+architecture psl of issue is
+
+  attribute anyconst : boolean;
+  signal a: natural;
+  attribute anyconst of a : signal is true;
+
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- works
+  assume always a = 42;
+  assert always a = 42;
+
+end architecture;
diff --git a/testsuite/synth/issue1658/testsuite.sh b/testsuite/synth/issue1658/testsuite.sh
new file mode 100755
index 000000000..e2b84e95e
--- /dev/null
+++ b/testsuite/synth/issue1658/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only issue_1658
+count=$(grep -c gate_anyconst syn_issue_1658.vhdl)
+test $count -eq 3
+
+echo "Test successful"