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authorTristan Gingold <tgingold@free.fr>2019-12-24 17:49:46 +0100
committerTristan Gingold <tgingold@free.fr>2019-12-24 17:49:46 +0100
commit1ef6a4011c1c207c7a295148f09b3f403fd87d56 (patch)
tree10532c35848882a03225475bff31282df701eb38 /testsuite
parentbd8009927349fb4a4050104bc61f2e249d646240 (diff)
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testsuite/synth: add test for #1021
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue1021/tb_test.vhdl97
-rw-r--r--testsuite/synth/issue1021/test.vhdl51
-rw-r--r--testsuite/synth/issue1021/test1.vhdl51
-rwxr-xr-xtestsuite/synth/issue1021/testsuite.sh18
4 files changed, 217 insertions, 0 deletions
diff --git a/testsuite/synth/issue1021/tb_test.vhdl b/testsuite/synth/issue1021/tb_test.vhdl
new file mode 100644
index 000000000..8372b51fe
--- /dev/null
+++ b/testsuite/synth/issue1021/tb_test.vhdl
@@ -0,0 +1,97 @@
+entity tb_test is
+ generic(
+ ROW_BITS : integer := 4;
+ WIDTH : integer := 64
+ );
+end tb_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test is
+ signal clk : std_logic;
+ signal rd_addr : std_logic_vector(ROW_BITS - 1 downto 0);
+ signal rd_data : std_logic_vector(WIDTH - 1 downto 0);
+ signal wr_en : std_logic;
+ signal wr_sel : std_logic_vector(WIDTH/8 - 1 downto 0);
+ signal wr_addr : std_logic_vector(ROW_BITS - 1 downto 0);
+ signal wr_data : std_logic_vector(WIDTH - 1 downto 0);
+begin
+ dut: entity work.test
+ generic map (
+ ROW_BITS => ROW_BITS,
+ WIDTH => WIDTH)
+ port map (
+ clk => clk,
+ rd_addr => rd_addr,
+ rd_data => rd_data,
+ wr_en => wr_en,
+ wr_sel => wr_sel,
+ wr_addr => wr_addr,
+ wr_data => wr_data);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ rd_addr <= x"0";
+ wr_addr <= x"0";
+ wr_data <= x"01_23_45_67_89_ab_cd_ef";
+ wr_sel <= x"ff";
+ wr_en <= '1';
+ pulse;
+
+ -- Simple read.
+ rd_addr <= x"0";
+ -- And write at a different address.
+ wr_addr <= x"1";
+ wr_data <= x"ff_ee_dd_cc_bb_aa_99_88";
+ wr_en <= '1';
+ wr_sel <= x"ff";
+ pulse;
+ assert rd_data = x"01_23_45_67_89_ab_cd_ef" severity failure;
+
+ rd_addr <= x"1";
+ -- Partial write
+ wr_addr <= x"0";
+ wr_data <= x"00_ee_00_00_00_00_00_00";
+ wr_sel <= x"40";
+ pulse;
+ assert rd_data = x"ff_ee_dd_cc_bb_aa_99_88" severity failure;
+
+ -- Check result.
+ rd_addr <= x"0";
+ wr_en <= '0';
+ pulse;
+ assert rd_data = x"01_ee_45_67_89_ab_cd_ef" severity failure;
+
+ -- Check that read is synchronous with clock.
+ rd_addr <= x"1";
+ assert rd_data = x"01_ee_45_67_89_ab_cd_ef" severity failure;
+
+ -- Check that read occurs before write.
+ wr_addr <= x"1";
+ wr_data <= x"f0_00_00_00_00_00_00_00";
+ wr_sel <= x"80";
+ rd_addr <= x"1";
+ wr_en <= '1';
+ pulse;
+ assert rd_data = x"ff_ee_dd_cc_bb_aa_99_88" severity failure;
+
+ wr_en <= '0';
+ wr_data <= x"00_00_00_00_00_00_00_00";
+ wr_sel <= x"ff";
+ pulse;
+ assert rd_data = x"f0_ee_dd_cc_bb_aa_99_88" severity failure;
+
+ pulse;
+ assert rd_data = x"f0_ee_dd_cc_bb_aa_99_88" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1021/test.vhdl b/testsuite/synth/issue1021/test.vhdl
new file mode 100644
index 000000000..c0ef9a020
--- /dev/null
+++ b/testsuite/synth/issue1021/test.vhdl
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity test is
+ generic(
+ ROW_BITS : integer := 4;
+ WIDTH : integer := 64
+ );
+
+ port(
+ clk : in std_logic;
+ rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
+ rd_data : out std_logic_vector(WIDTH - 1 downto 0);
+ wr_en : in std_logic;
+ wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
+ wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
+ wr_data : in std_logic_vector(WIDTH - 1 downto 0)
+ );
+
+end test;
+
+architecture rtl of test is
+ constant SIZE : integer := 2**ROW_BITS;
+
+ type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
+ signal ram : ram_type;
+
+begin
+ process(clk)
+ variable lbit : integer range 0 to WIDTH - 1;
+ variable mbit : integer range 0 to WIDTH - 1;
+ variable widx : integer range 0 to SIZE - 1;
+ begin
+ if rising_edge(clk) then
+ if wr_en = '1' then
+ for i in 0 to WIDTH/8-1 loop
+ lbit := i * 8;
+ mbit := lbit + 7;
+ widx := to_integer(unsigned(wr_addr));
+ if wr_sel(i) = '1' then
+ ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
+ end if;
+ end loop;
+ end if;
+
+ rd_data <= ram(to_integer(unsigned(rd_addr)));
+ end if;
+ end process;
+end;
diff --git a/testsuite/synth/issue1021/test1.vhdl b/testsuite/synth/issue1021/test1.vhdl
new file mode 100644
index 000000000..2c66c2ef4
--- /dev/null
+++ b/testsuite/synth/issue1021/test1.vhdl
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity test is
+ generic(
+ ROW_BITS : integer := 8;
+ WIDTH : integer := 16
+ );
+
+ port(
+ clk : in std_logic;
+ rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
+ rd_data : out std_logic_vector(WIDTH - 1 downto 0);
+ wr_en : in std_logic;
+ wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
+ wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
+ wr_data : in std_logic_vector(WIDTH - 1 downto 0)
+ );
+
+end test;
+
+architecture rtl of test is
+ constant SIZE : integer := 2**ROW_BITS;
+
+ type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
+ signal ram : ram_type;
+
+begin
+ process(clk)
+ variable lbit : integer range 0 to WIDTH - 1;
+ variable mbit : integer range 0 to WIDTH - 1;
+ variable widx : integer range 0 to SIZE - 1;
+ begin
+ if rising_edge(clk) then
+ if wr_en = '1' then
+ for i in 0 to WIDTH/8-1 loop
+ lbit := i * 8;
+ mbit := lbit + 7;
+ widx := to_integer(unsigned(wr_addr));
+ if wr_sel(i) = '1' then
+ ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
+ end if;
+ end loop;
+ end if;
+
+ rd_data <= ram(to_integer(unsigned(rd_addr)));
+ end if;
+ end process;
+end;
diff --git a/testsuite/synth/issue1021/testsuite.sh b/testsuite/synth/issue1021/testsuite.sh
new file mode 100755
index 000000000..cca8f9080
--- /dev/null
+++ b/testsuite/synth/issue1021/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in test; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
+ clean
+done
+
+echo "Test successful"