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authorTristan Gingold <tgingold@free.fr>2019-11-07 06:18:47 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-07 06:18:47 +0100
commit20d538b26feca9b40476181b121ee64c7aabbf5a (patch)
tree6f32456aad816ca0f58b77a81c50d5a865fa815b /testsuite
parent5d644d6043dd16eb5619c169fa9145d47fdc5407 (diff)
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testsuite/synth: add testcase for or short-circuit. #1005
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue1005/test2.vhdl24
-rwxr-xr-xtestsuite/synth/issue1005/testsuite.sh7
2 files changed, 28 insertions, 3 deletions
diff --git a/testsuite/synth/issue1005/test2.vhdl b/testsuite/synth/issue1005/test2.vhdl
new file mode 100644
index 000000000..47d7d6071
--- /dev/null
+++ b/testsuite/synth/issue1005/test2.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use std.env.stop;
+
+entity test2 is
+ generic (
+ SIM : boolean := false
+ );
+ port (
+ val : in std_ulogic
+ );
+end entity test2;
+
+architecture behaviour of test2 is
+begin
+ process_0: process(all)
+ begin
+ if not SIM or val = '1' then
+ null;
+ else
+ stop;
+ end if;
+ end process;
+end architecture behaviour;
diff --git a/testsuite/synth/issue1005/testsuite.sh b/testsuite/synth/issue1005/testsuite.sh
index 5643f943a..4dffa0455 100755
--- a/testsuite/synth/issue1005/testsuite.sh
+++ b/testsuite/synth/issue1005/testsuite.sh
@@ -3,9 +3,10 @@
. ../../testenv.sh
GHDL_STD_FLAGS=--std=08
-t=test
-synth $t.vhdl -e $t > syn_$t.vhdl
-analyze syn_$t.vhdl
+for t in test test2; do
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl
+done
clean