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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-30 13:52:30 +0200 |
|---|---|---|
| committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-07-01 06:39:47 +0200 |
| commit | 301dea333ec3e28e95a43b1a4af569ebbedd6ab9 (patch) | |
| tree | acd83171832402e31c6a55dafdbb47afa43a1529 /testsuite | |
| parent | 12a6518bf4d2e41664210b77a5416eca0d1dc7af (diff) | |
| download | ghdl-301dea333ec3e28e95a43b1a4af569ebbedd6ab9.tar.gz ghdl-301dea333ec3e28e95a43b1a4af569ebbedd6ab9.tar.bz2 ghdl-301dea333ec3e28e95a43b1a4af569ebbedd6ab9.zip | |
Added package declarations inside of declarations.
Added PSL Default clock (dummy).
Added Disconnect specification (dummy).
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index b2c7aff11..93474000b 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -77,6 +77,13 @@ architecture behav of entity_1 is attribute att : boolean; alias bar is boolean; + + disconnect address_bus : resolved_word after 3 ns; + disconnect others : resolved_word after 2 ns; + + default clock is rising_edge(clk); + package inner_pack is + end package; begin process(Clock) begin @@ -100,7 +107,7 @@ package package_1 is type cell; constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3; - attribute fixed of ghdl [bar] : constant is true; + attribute fixed of ghdl, gtkwave [x, y] : constant is true; component comp is port ( |