Add testcase for previous patch

4 files changed, 187 insertions, 0 deletions

diff --git a/testsuite/gna/bug083/repro.vhdl b/testsuite/gna/bug083/repro.vhdl
new file mode 100644
index 000000000..970d0b694
--- /dev/null
+++ b/testsuite/gna/bug083/repro.vhdl
@@ -0,0 +1,79 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+end;
+
+architecture behav of repro is
+  type t_axilite_write_address_channel is record
+    --DUT inputs
+    awaddr  : std_logic_vector;
+    awvalid : std_logic;
+    awprot  : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
+    --DUT outputs
+    awready : std_logic;
+  end record;
+
+  type t_axilite_write_data_channel is record
+    --DUT inputs
+    wdata   : std_logic_vector;
+    wstrb   : std_logic_vector;
+    wvalid  : std_logic;
+    --DUT outputs
+    wready  : std_logic;
+  end record;
+
+  type t_axilite_write_response_channel is record
+    --DUT inputs
+    bready  : std_logic;
+    --DUT outputs
+    bresp   : std_logic_vector(1 downto 0);
+    bvalid  : std_logic;
+  end record;
+
+  type t_axilite_read_address_channel is record
+    --DUT inputs
+    araddr  : std_logic_vector;
+    arvalid : std_logic;
+    arprot  : std_logic_vector(2 downto 0);  -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
+    --DUT outputs
+    arready : std_logic;
+  end record;
+
+  type t_axilite_read_data_channel is record
+    --DUT inputs
+    rready  : std_logic;
+    --DUT outputs
+    rdata   : std_logic_vector;
+    rresp   : std_logic_vector(1 downto 0);
+    rvalid  : std_logic;
+  end record;
+
+  type t_axilite_if is record
+    write_address_channel  : t_axilite_write_address_channel;
+    write_data_channel     : t_axilite_write_data_channel;
+    write_response_channel : t_axilite_write_response_channel;
+    read_address_channel   : t_axilite_read_address_channel;
+    read_data_channel      : t_axilite_read_data_channel;
+  end record;
+
+  function get_w return natural is
+  begin
+    return 32;
+  end get_w;
+begin
+
+  process
+    constant addr_width : natural := get_w;
+    constant data_width : natural := get_w;
+
+    variable init_if : t_axilite_if
+      (  write_address_channel( awaddr( addr_width    -1 downto 0)), 
+         write_data_channel(    wdata(  data_width    -1 downto 0),
+                                wstrb(( data_width/8) -1 downto 0)),
+         read_address_channel(  araddr( addr_width    -1 downto 0)),
+         read_data_channel(     rdata(  data_width    -1 downto 0)));
+  begin
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/bug083/repro2.vhdl b/testsuite/gna/bug083/repro2.vhdl
new file mode 100644
index 000000000..e5a314194
--- /dev/null
+++ b/testsuite/gna/bug083/repro2.vhdl
@@ -0,0 +1,27 @@
+entity repro2 is
+end;
+
+architecture behav of repro2 is
+  type t_axilite_write_address_channel is record
+    awaddr  : bit_vector;
+  end record;
+
+  type t_axilite_if is record
+    write_address_channel  : t_axilite_write_address_channel;
+  end record;
+
+  function get_w return natural is
+  begin
+    return 32;
+  end get_w;
+begin
+
+  process
+    constant addr_width : natural := get_w;
+
+    variable init_if : t_axilite_if
+      (  write_address_channel( awaddr( addr_width    -1 downto 0)));
+  begin
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/bug083/repro3.vhdl b/testsuite/gna/bug083/repro3.vhdl
new file mode 100644
index 000000000..455609e5e
--- /dev/null
+++ b/testsuite/gna/bug083/repro3.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3 is
+end;
+
+architecture behav of repro3 is
+  type t_axilite_write_address_channel is record
+    --DUT inputs
+    awaddr  : std_logic_vector;
+    awvalid : std_logic;
+  end record;
+
+  type t_axilite_write_data_channel is record
+    --DUT inputs
+    wdata   : std_logic_vector;
+    wstrb   : std_logic_vector;
+    wvalid  : std_logic;
+    --DUT outputs
+    wready  : std_logic;
+  end record;
+
+  type t_axilite_read_address_channel is record
+    --DUT inputs
+    araddr  : std_logic_vector;
+    arvalid : std_logic;
+    arprot  : std_logic_vector(2 downto 0);
+    --DUT outputs
+    arready : std_logic;
+  end record;
+
+  type t_axilite_read_data_channel is record
+    --DUT inputs
+    rready  : std_logic;
+    --DUT outputs
+    rdata   : std_logic_vector;
+    rresp   : std_logic_vector(1 downto 0);
+    rvalid  : std_logic;
+  end record;
+
+  type t_axilite_if is record
+    write_address_channel  : t_axilite_write_address_channel;
+    write_data_channel     : t_axilite_write_data_channel;
+    read_address_channel   : t_axilite_read_address_channel;
+    read_data_channel      : t_axilite_read_data_channel;
+  end record;
+
+  function get_w return natural is
+  begin
+    return 32;
+  end get_w;
+begin
+
+  process
+    constant addr_width : natural := get_w;
+    constant data_width : natural := get_w;
+
+    variable init_if : t_axilite_if
+      (  write_address_channel( awaddr( addr_width    -1 downto 0)), 
+         write_data_channel(    wdata(  data_width    -1 downto 0),
+                                wstrb(( data_width/8) -1 downto 0)),
+         read_address_channel(  araddr( addr_width    -1 downto 0)),
+         read_data_channel(     rdata(  data_width    -1 downto 0)));
+  begin
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/bug083/testsuite.sh b/testsuite/gna/bug083/testsuite.sh
new file mode 100755
index 000000000..1493b0f92
--- /dev/null
+++ b/testsuite/gna/bug083/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro2.vhdl
+elab_simulate repro2
+
+analyze repro.vhdl
+elab_simulate repro
+
+clean
+
+echo "Test successful"