Add reproducer for #522

3 files changed, 204 insertions, 0 deletions

diff --git a/testsuite/gna/issue522/shifter.vhdl b/testsuite/gna/issue522/shifter.vhdl
new file mode 100644
index 000000000..9ef1a31b9
--- /dev/null
+++ b/testsuite/gna/issue522/shifter.vhdl
@@ -0,0 +1,65 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+entity Shifter is
+port(shift_lsl :in std_logic;
+        shift_lsr :in std_logic;
+        shift_asr :in std_logic;
+        shift_ror :in std_logic;
+        shift_rrx :in std_logic;
+        cin       :in std_logic;
+        shift_val :in std_logic_vector (4 downto 0);
+        din       :in std_logic_vector(31 downto 0);     
+        dout      :out std_logic_vector(31 downto 0);
+        cout      :out std_logic;
+        vdd       :in bit;
+        vss       :in bit);
+end Shifter;
+
+architecture ArchiShifter of Shifter is
+    signal res1, res2, res3, res4, res5, res6, res7 : std_logic_vector(31 downto 0):=x"00000000";
+    signal carryOut: std_logic;
+
+    begin
+        --LSL & LSR & ASR
+        res1 <= din(30 downto 0) & '0'      when shift_val(0)='1'  and             shift_lsl='1'                           else 
+                '0' & din(31 downto 1)      when shift_val(0)='1'  and (shift_lsr='1' or (shift_asr='1' and din(31)='0'))  else
+                '1' & din(31 downto 1)      when shift_val(0)='1'  and (shift_asr='1' and din(31)='1' )                    else din;
+
+        res2 <= res1(29 downto 0) & "00"    when shift_val(1)='1'  and             shift_lsl='1'                           else
+                "00" & res1(31 downto 2)    when shift_val(1)='1'  and (shift_lsr='1' or (shift_asr='1' and din(31)='0'))  else
+                "11" & res1(31 downto 2)    when shift_val(1)='1'  and (shift_asr='1'and din(31)='1' )                     else res1;
+             
+        res3 <= res2(27 downto 0) & x"0"    when shift_val(2)='1'  and             shift_lsl='1'                           else 
+                x"0" & res2(31 downto 4)    when shift_val(2)='1'  and (shift_lsr='1' or (shift_asr='1' and din(31)='0'))  else 
+                x"F" & res2(31 downto 4)    when shift_val(2)='1'  and (shift_asr='1'and din(31)='1' )                     else res2;
+
+        res4 <= res3(23 downto 0) & x"00"   when shift_val(3)='1'  and             shift_lsl='1'                           else 
+                x"00" & res3(31 downto 8)   when shift_val(3)='1'  and (shift_lsr='1' or (shift_asr='1' and din(31)='0'))  else
+                x"FF" & res3(31 downto 8)   when shift_val(3)='1'  and (shift_asr='1' and din(31)='1' )                    else res3;
+
+        res5 <= res4(15 downto 0) & x"0000" when shift_val(4)='1'  and             shift_lsl='1'                           else 
+               x"0000" & res4(31 downto 16) when shift_val(4)='1'  and (shift_lsr='1' or (shift_asr='1' and din(31)='0'))  else
+               x"FFFF" & res4(31 downto 16) when shift_val(4)='1'  and (shift_asr='1' and din(31)='1' )                    else res4;
+                
+        carryOut <= din(32-to_integer(unsigned(shift_val))) when shift_val /="00000" and shift_lsl='1' else 
+                    din(to_integer(unsigned(shift_val))-1)  when shift_val /="00000" and (shift_lsr='1' or shift_asr='1' or shift_ror='1') else
+                    din(0) when shift_rrx='1' else cin; 
+        --RRX
+        res6 <= cin & din(31 downto 1) when shift_rrx='1' else din;
+
+        --ROR
+        res7(31 downto (32-to_integer(unsigned(shift_val)))) <= din((to_integer(unsigned(shift_val))-1) downto 0) when shift_ror='1' and shift_val /="00000" 
+                                                                else din; 
+        res7((31-to_integer(unsigned(shift_val))) downto 0)  <= din(31 downto to_integer(unsigned(shift_val)))    when shift_ror='1' and shift_val /="00000" 
+                                                                else din;
+
+
+        dout <= res5 when shift_lsl='1' or shift_asr='1' or shift_lsr='1' else
+                res6 when shift_rrx='1' else
+                res7 when shift_ror='1' else
+                din;
+        cout <= carryOut;
+
+end ArchiShifter;
diff --git a/testsuite/gna/issue522/shifter_tb.vhdl b/testsuite/gna/issue522/shifter_tb.vhdl
new file mode 100644
index 000000000..3a95478c8
--- /dev/null
+++ b/testsuite/gna/issue522/shifter_tb.vhdl
@@ -0,0 +1,128 @@
+library ieee;
+use ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity Shifter_tb is
+end Shifter_tb;
+
+architecture simu of Shifter_tb is
+        signal shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx, cin : std_logic;
+        signal shift_val   :std_logic_vector (4 downto 0);
+        signal din         :std_logic_vector (31 downto 0);     
+        signal dout        :std_logic_vector (31 downto 0);
+        signal cout        :std_logic;
+        signal vdd         :bit;
+        signal vss         :bit;
+begin
+
+    L0: entity work.Shifter
+	port map (shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx, cin, shift_val, din, dout,cout, vdd, vss);
+	process
+        variable test : std_logic_vector (31 downto 0);
+        constant exttest : std_logic_vector (31 downto 0) := X"FFFFFFFF";
+	begin
+        cin       <= '0';
+        shift_val <= "00000";
+        din       <= X"0FF00000";
+        shift_asr <= '0';
+        shift_ror <= '0';
+        shift_rrx <= '0';
+        shift_lsl <= '0';
+        shift_lsr <= '0'; 
+       	assert  dout = din report  "Variable Test = Initial Defaut"severity error;
+      	wait for 1 ns;
+
+--*************************************ASR**************************************************
+            din <= X"A5A50000";
+            shift_asr <= '0';
+            shift_ror <= '1';
+            shift_rrx <= '0';
+            shift_lsl <= '0';
+            shift_lsr <= '0';
+
+            for shift in 0 to 30 looP
+                shift_val <= std_logic_vector(to_unsigned(shift,5 ));
+                test := din;
+                wait for 1 ns;
+                if shift /= 0 then
+                    --"asr" équivaut à une division signé par "2^shift"
+                    --l'operateur exposant n'étant pas disponible on fais une boucle qui divise par 2^shift à chaque tour de boucle   
+                    for i in 0 to (shift-1) loop
+                        test := std_logic_vector (shift_right(signed(test),1));
+                        assert  dout = test  report "Expected Test Result  = " & integer'image(to_integer(signed(test))) & " || Dout  = " & 
+                        integer'image(to_integer(signed(dout))) & " || ASR shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
+                    end loop; 
+                else
+                    test := std_logic_vector(signed(din));      
+                    assert  dout = test report "Expected Test Result  = " & integer'image(to_integer(signed(test))) & 
+                    " || Dout = " & integer'image(to_integer(signed(dout))) & " ||ASR shift = " & integer'image(shift) severity error;
+                end if;
+                wait for 2 ns;  
+            end loop;
+
+--Test de l'extention de signe
+        din       <= X"80000000";
+        shift_val <= "11111";
+wait for 1 ns; 
+assert  dout (31 downto 0) =  exttest (31 downto 0)  report "Bit de Signe = " & integer'image ( to_integer (unsigned(din(31 downto 31)))) & " || Dout  =" & integer'image(to_integer(unsigned(dout (31 downto (31-(to_integer(unsigned(shift_val)))))))) & " || ASR shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
+
+--*************************************LSR**************************************************
+            cin <= '0';
+            shift_lsr <= '1';
+            shift_asr <= '0';
+            shift_ror <= '0';
+            shift_rrx <= '0';
+       	    shift_lsl <= '0';
+
+            for shift in 0 to 30 looP
+                shift_val <= std_logic_vector(to_unsigned(shift, 5 ));
+                test := din;
+                wait for 1 ns;
+                if shift /= 0 then
+                    for i in 0 to (shift-1) loop
+                        test := std_logic_vector (shift_right(unsigned(test),1));
+                        assert  dout = test  report "Expected Test Result  = " & integer'image(to_integer(unsigned(test))) &  " || Dout  = " & 
+                        integer'image(to_integer(unsigned(dout))) & " || LSR shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
+                    end loop; 
+                else
+                    test := std_logic_vector(signed(din));      
+                    assert  dout = test report "Expected Test Result  = " & integer'image(to_integer(unsigned(test))) & 
+                    " || Dout = " & integer'image(to_integer(unsigned(dout))) & " || LSR shift = " & integer'image(shift) severity error;
+                end if;
+                wait for 2 ns;  
+            end loop;
+
+--*************************************LSL**************************************************
+            din <= X"F000A5A5";
+            shift_asr <= '0';
+            shift_ror <= '0';
+            shift_rrx <= '0';
+            shift_lsl <= '1';
+            shift_lsr <= '0';
+
+        for z in 0 to 256 loop
+            for shift in 0 to 30 loop
+	            shift_val <= std_logic_vector(to_unsigned(shift,5));
+                test := din;
+                wait for 1 ns;
+                if shift /= 0 then
+                    for i in 0 to (shift-1) loop
+                        test := std_logic_vector (shift_left(unsigned(test),1));
+                        assert dout = test report "Expected Test Result  = " & integer'image(to_integer(unsigned(test))) & " || Dout  = " & 
+                        integer'image(to_integer(unsigned(dout))) & " ||LSL shift = " & integer'image(to_integer(unsigned(shift_val))) severity error; 
+                    end loop;
+                else
+                    test := std_logic_vector(unsigned(din));      
+                    assert  dout = test report "Expected Test Result  = " & integer'image(to_integer(unsigned(test))) & 
+                    " || Dout = " & integer'image(to_integer(unsigned(dout))) & " || LSR shift = " & integer'image(shift) severity error;
+                end if; 
+                wait for 2 ns;  
+	        end loop;
+        end loop;	  
+
+--**********************************************************************************************	    
+    report "end of TB";
+    wait for 4 ns;
+    wait;
+  end process;
+end simu;
diff --git a/testsuite/gna/issue522/testsuite.sh b/testsuite/gna/issue522/testsuite.sh
new file mode 100755
index 000000000..6f1b868d3
--- /dev/null
+++ b/testsuite/gna/issue522/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze shifter.vhdl
+analyze shifter_tb.vhdl
+elab_simulate_failure shifter_tb
+
+clean
+
+echo "Test successful"