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author | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:34:17 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:34:17 +0100 |
commit | 556bd7c420a231b02b7159217aec9ae5bbe34e8d (patch) | |
tree | 0f434f2bfa2a777f81ffb90e5da896de8bb179e0 /testsuite | |
parent | 2e50c44a48b74ecb7f5a14e4c4d0181cfa2d7402 (diff) | |
download | ghdl-556bd7c420a231b02b7159217aec9ae5bbe34e8d.tar.gz ghdl-556bd7c420a231b02b7159217aec9ae5bbe34e8d.tar.bz2 ghdl-556bd7c420a231b02b7159217aec9ae5bbe34e8d.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/if02/if01.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/if02/if02.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/if02/if03.vhdl | 21 | ||||
-rwxr-xr-x | testsuite/synth/if02/testsuite.sh | 9 | ||||
-rw-r--r-- | testsuite/testenv.sh | 10 |
5 files changed, 70 insertions, 0 deletions
diff --git a/testsuite/synth/if02/if01.vhdl b/testsuite/synth/if02/if01.vhdl new file mode 100644 index 000000000..fa515cd7d --- /dev/null +++ b/testsuite/synth/if02/if01.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity if01 is + port (a : std_logic; + b : std_logic; + sel : std_logic; + s : out std_logic); +end if01; + +architecture behav of if01 is +begin + s <= a when sel = '0' + else b when sel = '1'; +end behav; diff --git a/testsuite/synth/if02/if02.vhdl b/testsuite/synth/if02/if02.vhdl new file mode 100644 index 000000000..b9155c7c4 --- /dev/null +++ b/testsuite/synth/if02/if02.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity if01 is + port (a : std_logic; + b : std_logic; + sel : std_logic_vector (1 downto 0); + s : out std_logic); +end if01; + +architecture behav of if01 is +begin + s <= a when sel = "01" + else b when sel = "10"; +end behav; diff --git a/testsuite/synth/if02/if03.vhdl b/testsuite/synth/if02/if03.vhdl new file mode 100644 index 000000000..6ff896358 --- /dev/null +++ b/testsuite/synth/if02/if03.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity if03 is + port (a : std_logic; + b : std_logic; + sel : std_logic; + s : out std_logic); +end if03; + +architecture behav of if03 is +begin + process (a, b, sel) + begin + if sel = '0' then + s <= a; + elsif sel = '1' then + s <= b; + end if; + end process; +end behav; diff --git a/testsuite/synth/if02/testsuite.sh b/testsuite/synth/if02/testsuite.sh new file mode 100755 index 000000000..575200dcb --- /dev/null +++ b/testsuite/synth/if02/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in if01 if02 if03; do + synth_failure $t.vhdl -e +done + +echo "Test successful" diff --git a/testsuite/testenv.sh b/testsuite/testenv.sh index d95644dc3..c3b6f6556 100644 --- a/testsuite/testenv.sh +++ b/testsuite/testenv.sh @@ -109,6 +109,16 @@ synth() "$GHDL" --synth $GHDL_STD_FLAGS $GHDL_FLAGS $@ } +synth_failure () +{ + echo "try to synthesize $@" + # for arg in $@; do echo "arg: $arg"; done + if ! "$GHDL" --synth --expect-failure $GHDL_STD_FLAGS $GHDL_FLAGS "$@" ; then + echo "Failure expected" + return 1 + fi +} + # Synthesis of a single file and analyze the result synth_analyze() { |