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authorTristan Gingold <tgingold@free.fr>2020-03-01 11:48:48 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-01 11:48:48 +0100
commit63b7d214239ec994258153d8fbccf59d07b4ea26 (patch)
tree827e3978e1fa886a569f71e2074440cfc7cf4dd5 /testsuite
parentb8ea7696f5e7fee31fb39c13e08a241514caecd4 (diff)
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testsuite/gna: add a test for #1138
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/issue1138/crc_pkg.vhdl53
-rw-r--r--testsuite/gna/issue1138/repro.vhdl17
-rwxr-xr-xtestsuite/gna/issue1138/testsuite.sh16
-rw-r--r--testsuite/gna/issue1138/wbcrc_syn.vhdl47
4 files changed, 133 insertions, 0 deletions
diff --git a/testsuite/gna/issue1138/crc_pkg.vhdl b/testsuite/gna/issue1138/crc_pkg.vhdl
new file mode 100644
index 000000000..ca8d93079
--- /dev/null
+++ b/testsuite/gna/issue1138/crc_pkg.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use ieee.math_real.all;
+
+package crc_pkg is
+
+ type crcParam_t is record
+ selLen : integer;
+ poly : std_ulogic_vector;
+ iniVect : std_ulogic_vector;
+ refIn : boolean;
+ refOut : boolean;
+ xorOut : std_ulogic_vector;
+ end record;
+
+ pure function getCrc32Param( stdCrc : string
+ ; datLen : integer
+ ) return crcParam_t;
+
+end crc_pkg;
+
+package body crc_pkg is
+
+ pure function getCrc32Param( stdCrc : string
+ ; datLen : integer
+ ) return crcParam_t is
+ variable crcParam_v : crcParam_t( poly ( 31 downto 0)
+ , iniVect ( 31 downto 0)
+ , xorOut ( 31 downto 0) );
+ begin
+ if ( "CRC-32/CCITT-FALSE" = stdCrc ) then
+ crcParam_v.selLen := datLen / 8 ;
+ crcParam_v.poly := X"04C11DB7" ;
+ crcParam_v.iniVect := X"FFFFFFFF" ;
+ crcParam_v.refIn := true ;
+ crcParam_v.refOut := true ;
+ crcParam_v.xorOut := X"FFFFFFFF" ;
+ else
+ crcParam_v.selLen := datLen / 8 ;
+ crcParam_v.poly := X"000000AF" ;
+ crcParam_v.iniVect := X"00000000" ;
+ crcParam_v.refIn := false ;
+ crcParam_v.refOut := false ;
+ crcParam_v.xorOut := X"00000000" ;
+ assert false report
+ " Standard crc not implemented Yet."
+ severity failure;
+ end if;
+ return crcParam_v;
+ end function;
+
+end package body crc_pkg;
diff --git a/testsuite/gna/issue1138/repro.vhdl b/testsuite/gna/issue1138/repro.vhdl
new file mode 100644
index 000000000..31d273f75
--- /dev/null
+++ b/testsuite/gna/issue1138/repro.vhdl
@@ -0,0 +1,17 @@
+entity repro is
+end;
+
+architecture behav of repro is
+ type my_rec is record
+ bv : bit_vector;
+ end record;
+
+ function get_bv (n : natural) return my_rec is
+ begin
+ return (bv => (1 to n => '0'));
+ end get_bv;
+
+ constant l : natural := get_bv (5).bv'length;
+begin
+ assert l = 5;
+end;
diff --git a/testsuite/gna/issue1138/testsuite.sh b/testsuite/gna/issue1138/testsuite.sh
new file mode 100755
index 000000000..e67643f7b
--- /dev/null
+++ b/testsuite/gna/issue1138/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze_failure repro.vhdl
+analyze_failure crc_pkg.vhdl wbcrc_syn.vhdl
+
+export GHDL_STD_FLAGS="--std=08 -frelaxed"
+analyze repro.vhdl
+elab_simulate repro
+analyze crc_pkg.vhdl wbcrc_syn.vhdl
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue1138/wbcrc_syn.vhdl b/testsuite/gna/issue1138/wbcrc_syn.vhdl
new file mode 100644
index 000000000..c90e162f3
--- /dev/null
+++ b/testsuite/gna/issue1138/wbcrc_syn.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use IEEE.MATH_REAL.all;
+
+--library ghdl_test;
+-- use ghdl_test.crc_pkg.all;
+ use work.crc_pkg.all;
+
+entity wbCrc_syn is
+ generic( yes_G : std_logic :='1'
+ ; fClkSys_Hz_G : integer := 100e6
+ ; isSimul_G : boolean := false
+ ; wbDataWidth_G : integer := 8
+ ; wbAddrWidth_G : integer := 32
+ ; wbTgaWidth_G : integer := 1
+ ; wbTgcWidth_G : integer := 1
+ ; wbTgdWidth_G : integer := 1
+ ; crcDefault_G : String := "CRC-32/CCITT-FALSE"
+ );
+ port( clk_i : in std_ulogic;
+
+ rx_is_dat_i : in std_ulogic_vector( wbDataWidth_G - 1 downto 0 );
+ rx_is_adr_i : in std_ulogic_vector( wbAddrWidth_G - 1 downto 0 );
+ rx_is_sel_i : in std_ulogic_vector( wbDataWidth_G / 8 - 1 downto 0 );
+ rx_is_loc_i : in std_ulogic;
+ rx_is_cyc_i : in std_ulogic;
+ rx_is_stb_i : in std_ulogic;
+ rx_is_we_i : in std_ulogic;
+ rx_os_ack_o : out std_ulogic;
+ rx_os_stl_o : out std_ulogic;
+ rx_os_err_o : out std_ulogic;
+
+ tx_os_cyc_o : out std_ulogic;
+ tx_os_stb_o : out std_ulogic;
+ tx_os_we_o : out std_ulogic;
+ tx_os_dat_o : out std_ulogic_vector( getCrc32Param( crcDefault_G , 8 ).poly'length - 1 downto 0 );
+ tx_os_cti_o : out std_ulogic_vector(2 downto 0) ;
+ tx_os_sel_o : out std_ulogic_vector( wbDataWidth_G / 8 - 1 downto 0 );
+ tx_os_loc_o : out std_ulogic;
+ tx_is_ack_i : in std_ulogic
+ );
+end wbCrc_syn;
+architecture rtl of wbCrc_syn is
+begin
+
+end rtl;