Add testcase for #530

3 files changed, 106 insertions, 0 deletions

diff --git a/testsuite/gna/issue530/repro2.vhdl b/testsuite/gna/issue530/repro2.vhdl
new file mode 100644
index 000000000..77cc0105e
--- /dev/null
+++ b/testsuite/gna/issue530/repro2.vhdl
@@ -0,0 +1,49 @@
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.numeric_std.all;
+
+entity submodule is
+port (
+   clk : in  std_logic;
+   arg : in  std_logic_vector(15 downto 0);
+   res : out std_logic_vector(15 downto 0)
+);
+end submodule;
+
+architecture behav of submodule is
+begin
+end behav;
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.numeric_std.all;
+
+entity sliced_ex is
+port (
+   clk   : in  std_logic;
+   arg_a : in  signed(7 downto 0);
+   arg_b : in  signed(7 downto 0);
+   res_a : out signed(7 downto 0);
+   res_b : out signed(7 downto 0)
+);
+end sliced_ex;
+
+architecture rtl of sliced_ex is
+
+   signal tmp : signed(15 downto 0);
+
+begin
+
+   SUB_MODULE : entity work.submodule
+   port map (
+      clk => clk,
+      arg( 7 downto 0) => std_logic_vector(arg_a),
+      arg(15 downto 8) => std_logic_vector(arg_b),
+      -- The casting of a sliced output causes an exception.
+      -- Casting of the entire output bus does work
+      -- signed(res) => tmp -- (this would work)
+      signed(res( 7 downto 0)) => res_a,
+      signed(res(15 downto 8)) => res_b
+   );
+
+end rtl;
diff --git a/testsuite/gna/issue530/sample_slice_ports.vhdl b/testsuite/gna/issue530/sample_slice_ports.vhdl
new file mode 100644
index 000000000..2820149b4
--- /dev/null
+++ b/testsuite/gna/issue530/sample_slice_ports.vhdl
@@ -0,0 +1,45 @@
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.numeric_std.all;
+
+entity submodule is
+port (
+   clk : in  std_logic;
+   arg : in  std_logic_vector(15 downto 0);
+   res : out std_logic_vector(15 downto 0)
+);
+end submodule;
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.numeric_std.all;
+
+entity sliced_ex is
+port (
+   clk   : in  std_logic;
+   arg_a : in  signed(7 downto 0);
+   arg_b : in  signed(7 downto 0);
+   res_a : out signed(7 downto 0);
+   res_b : out signed(7 downto 0)
+);
+end sliced_ex;
+
+architecture rtl of sliced_ex is
+
+   signal tmp : signed(15 downto 0);
+
+begin
+
+   SUB_MODULE : entity work.submodule
+   port map (
+      clk => clk,
+      arg( 7 downto 0) => std_logic_vector(arg_a),
+      arg(15 downto 8) => std_logic_vector(arg_b),
+      -- The casting of a sliced output causes an exception.
+      -- Casting of the entire output bus does work
+      -- signed(res) => tmp -- (this would work)
+      signed(res( 7 downto 0)) => res_a,
+      signed(res(15 downto 8)) => res_b
+   );
+
+end rtl;
diff --git a/testsuite/gna/issue530/testsuite.sh b/testsuite/gna/issue530/testsuite.sh
new file mode 100755
index 000000000..b01358007
--- /dev/null
+++ b/testsuite/gna/issue530/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze sample_slice_ports.vhdl
+
+analyze repro2.vhdl
+elab_simulate sliced_ex
+
+clean
+
+echo "Test successful"