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authorTristan Gingold <tgingold@free.fr>2019-09-11 06:31:39 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-11 06:37:28 +0200
commit86480bfed6bce483936d585498e1498d8fde208d (patch)
tree66320d378a31c7ab467265f1f92bfbad8e004041 /testsuite
parentdb5c3b1cf051d215ee7f02064464b4b1088ea226 (diff)
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testsuite/synth: add ret01 tests.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/ret01/ret01.vhdl20
-rw-r--r--testsuite/synth/ret01/ret02.vhdl19
-rw-r--r--testsuite/synth/ret01/ret05.vhdl21
-rw-r--r--testsuite/synth/ret01/tb_ret01.vhdl26
-rw-r--r--testsuite/synth/ret01/tb_ret02.vhdl26
-rwxr-xr-xtestsuite/synth/ret01/testsuite.sh16
-rwxr-xr-xtestsuite/synth/simple01/testsuite.sh2
7 files changed, 129 insertions, 1 deletions
diff --git a/testsuite/synth/ret01/ret01.vhdl b/testsuite/synth/ret01/ret01.vhdl
new file mode 100644
index 000000000..64e7319f1
--- /dev/null
+++ b/testsuite/synth/ret01/ret01.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ret01 is
+ port (di : std_logic_vector (7 downto 0);
+ res : out integer);
+end ret01;
+
+architecture behav of ret01 is
+ function sign (v : std_logic_vector (7 downto 0)) return integer is
+ begin
+ if v (7) = '1' then
+ return -1;
+ else
+ return 1;
+ end if;
+ end sign;
+begin
+ res <= sign (di);
+end behav;
diff --git a/testsuite/synth/ret01/ret02.vhdl b/testsuite/synth/ret01/ret02.vhdl
new file mode 100644
index 000000000..8da4f3012
--- /dev/null
+++ b/testsuite/synth/ret01/ret02.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ret02 is
+ port (di : std_logic_vector (7 downto 0);
+ res : out integer);
+end ret02;
+
+architecture behav of ret02 is
+ function sign (v : std_logic_vector (7 downto 0)) return integer is
+ begin
+ if v (7) = '1' then
+ return -1;
+ end if;
+ return 1;
+ end sign;
+begin
+ res <= sign (di);
+end behav;
diff --git a/testsuite/synth/ret01/ret05.vhdl b/testsuite/synth/ret01/ret05.vhdl
new file mode 100644
index 000000000..c14e36d11
--- /dev/null
+++ b/testsuite/synth/ret01/ret05.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ret02 is
+ port (di : std_logic_vector (7 downto 0);
+ res : out integer);
+end ret02;
+
+architecture behav of ret02 is
+ function ffs (v : std_logic_vector (7 downto 0)) return integer is
+ begin
+ for i in v'range loop
+ if v (i) = '1' then
+ return i;
+ end if;
+ end loop;
+ return -1;
+ end ffs;
+begin
+ res <= ffs (di);
+end behav;
diff --git a/testsuite/synth/ret01/tb_ret01.vhdl b/testsuite/synth/ret01/tb_ret01.vhdl
new file mode 100644
index 000000000..469164c32
--- /dev/null
+++ b/testsuite/synth/ret01/tb_ret01.vhdl
@@ -0,0 +1,26 @@
+entity tb_ret01 is
+end tb_ret01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ret01 is
+ signal d : std_logic_vector (7 downto 0);
+ signal r : integer;
+begin
+ dut: entity work.ret01
+ port map (d, r);
+
+ process
+ begin
+ d <= x"01";
+ wait for 1 ns;
+ assert r = 1 severity failure;
+
+ d <= x"f1";
+ wait for 1 ns;
+ assert r = -1 severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/ret01/tb_ret02.vhdl b/testsuite/synth/ret01/tb_ret02.vhdl
new file mode 100644
index 000000000..a9f56c4d1
--- /dev/null
+++ b/testsuite/synth/ret01/tb_ret02.vhdl
@@ -0,0 +1,26 @@
+entity tb_ret02 is
+end tb_ret02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ret02 is
+ signal d : std_logic_vector (7 downto 0);
+ signal r : integer;
+begin
+ dut: entity work.ret02
+ port map (d, r);
+
+ process
+ begin
+ d <= x"01";
+ wait for 1 ns;
+ assert r = 1 severity failure;
+
+ d <= x"f1";
+ wait for 1 ns;
+ assert r = -1 severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/ret01/testsuite.sh b/testsuite/synth/ret01/testsuite.sh
new file mode 100755
index 000000000..40105e0be
--- /dev/null
+++ b/testsuite/synth/ret01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ret01 ret02; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
+ clean
+done
+
+echo "Test successful"
diff --git a/testsuite/synth/simple01/testsuite.sh b/testsuite/synth/simple01/testsuite.sh
index 3f7fd19d9..564b47fc4 100755
--- a/testsuite/synth/simple01/testsuite.sh
+++ b/testsuite/synth/simple01/testsuite.sh
@@ -9,7 +9,7 @@ for t in simple01; do
synth $t.vhdl -e $t > syn_$t.vhdl
analyze syn_$t.vhdl tb_$t.vhdl
- elab_simulate tb_$t
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
clean
done