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authorPatrick Lehmann <Patrick.Lehmann@plc2.de>2021-08-17 20:14:13 +0200
committerumarcor <unai.martinezcorral@ehu.eus>2021-08-23 16:35:36 +0200
commit8c0f8e0ad95c53beac983546550222117c6a639c (patch)
tree650acf22884b74848bce6eb63f98d64eea442de0 /testsuite
parentf8d7ac62564e4bdefb35e58178c4df1b4feae844 (diff)
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-rw-r--r--testsuite/pyunit/Current.vhdl20
1 files changed, 15 insertions, 5 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index 1f802af47..81887ae7f 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -136,20 +136,29 @@ begin
inst1: entity work.counter1(rtl)
generic map (
- BITS => 8
+ BITS1 => 8
)
port map (
- clk => Clock
+ clk1 => Clock
);
inst2: component counter2
+ generic map (
+ BITS2 => 8,
+ value2
+ )
port map (
- clk => Clock
+ clk2 => Clock,
+ enable2
);
inst3: configuration counter3
+ generic map (
+ BITS3 => 8
+ )
port map (
- clk => Clock
+ clk3 => Clock,
+ control(0) => battery and emergency
);
blk: block
@@ -215,7 +224,8 @@ begin
end block;
end generate;
- call: OtherDummy;
+ call: CallDummy;
+ called: CalledDummy(25);
ende: std.env.stop;
end architecture behav;