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| author | Tristan Gingold <tgingold@free.fr> | 2018-02-06 06:00:55 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-02-06 06:00:55 +0100 |
| commit | 8c9447bad365140e56415e1cc510964ef77b52a8 (patch) | |
| tree | 60fff6a4a619bb8e3d79aa95bf5814e31824bf4c /testsuite | |
| parent | f262f19da225ee875dccea38c66ac42df8d32fb4 (diff) | |
| download | ghdl-8c9447bad365140e56415e1cc510964ef77b52a8.tar.gz ghdl-8c9447bad365140e56415e1cc510964ef77b52a8.tar.bz2 ghdl-8c9447bad365140e56415e1cc510964ef77b52a8.zip | |
Add testcase for #525
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/gna/issue525/counter_illegal_attribute.vhd | 49 | ||||
| -rw-r--r-- | testsuite/gna/issue525/repro1.vhdl | 28 | ||||
| -rwxr-xr-x | testsuite/gna/issue525/testsuite.sh | 21 |
3 files changed, 98 insertions, 0 deletions
diff --git a/testsuite/gna/issue525/counter_illegal_attribute.vhd b/testsuite/gna/issue525/counter_illegal_attribute.vhd new file mode 100644 index 000000000..559958857 --- /dev/null +++ b/testsuite/gna/issue525/counter_illegal_attribute.vhd @@ -0,0 +1,49 @@ +--
+-- <counter.vhd>
+--
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+
+entity counter is
+
+ port
+ (
+ clk : in std_logic;
+ rst : in std_logic;
+
+ data_out : out std_logic_vector(7 downto 0)
+ );
+
+end counter;
+
+
+architecture arch1 of counter is
+
+ --
+ -- NOTE: placing port attributes here in the architecture body is illegal in VHDL,
+ -- but unfortunately Vivado requires them here to parse the X_INTERFACE attributes
+ --
+ attribute X_INTERFACE_INFO : string;
+ attribute X_INTERFACE_PARAMETER : string;
+
+ attribute X_INTERFACE_INFO of rst : signal is "xilinx.com:signal:reset:1.0 rst RST";
+ attribute X_INTERFACE_PARAMETER of rst : signal is "POLARITY ACTIVE_HIGH";
+
+ --
+ -- attempt to place attribute on non-existent signal
+ --
+ attribute X_INTERFACE_PARAMETER of no_such : signal is "POLARITY ACTIVE_HIGH";
+
+
+ signal count : unsigned(7 downto 0);
+
+begin
+
+ count <= (others => '0') when rst = '1' else count + 1 when rising_edge(clk);
+
+ data_out <= std_logic_vector(count);
+
+end arch1;
+
diff --git a/testsuite/gna/issue525/repro1.vhdl b/testsuite/gna/issue525/repro1.vhdl new file mode 100644 index 000000000..3fc5e2e96 --- /dev/null +++ b/testsuite/gna/issue525/repro1.vhdl @@ -0,0 +1,28 @@ +entity repro is
+ port
+ (
+ clk : in bit;
+ rst : in bit;
+
+ data_out : out bit_vector(7 downto 0)
+ );
+end ;
+
+
+architecture arch1 of repro is
+
+ --
+ -- NOTE: placing port attributes here in the architecture body is illegal in VHDL,
+ -- but unfortunately Vivado requires them here to parse the X_INTERFACE attributes
+ --
+ attribute X_INTERFACE_INFO : string;
+ attribute X_INTERFACE_PARAMETER : string;
+
+ attribute X_INTERFACE_INFO of rst : signal is "xilinx.com:signal:reset:1.0 rst RST";
+ attribute X_INTERFACE_PARAMETER of rst : signal is "POLARITY ACTIVE_HIGH";
+
+begin
+
+
+end arch1;
+
diff --git a/testsuite/gna/issue525/testsuite.sh b/testsuite/gna/issue525/testsuite.sh new file mode 100755 index 000000000..3f4cb11e8 --- /dev/null +++ b/testsuite/gna/issue525/testsuite.sh @@ -0,0 +1,21 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure counter_illegal_attribute.vhd + +# By default, emit only a warning when trying to specify an attribute for a +# port from the architecture. +analyze repro1.vhdl + +# Or in relaxed mode +export GHDL_STD_FLAGS="--std=93 -frelaxed-rules" +analyze repro1.vhdl + +# But it is an error in strict mode +export GHDL_STD_FLAGS=--std=93 +analyze_failure repro1.vhdl + +clean + +echo "Test successful" |