testsuite/gna: add a test for #2407

3 files changed, 93 insertions, 0 deletions

diff --git a/testsuite/gna/issue2407/shift_register.vhdl b/testsuite/gna/issue2407/shift_register.vhdl
new file mode 100644
index 000000000..e96fc7cea
--- /dev/null
+++ b/testsuite/gna/issue2407/shift_register.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity shift_register is
+  generic (
+    -- number of stages
+    NUM_STAGES: natural := 11;
+    -- number of bits
+    BITS: natural := 4
+  );
+  port (
+    clk, rst: in std_logic;
+    x: in std_logic_vector (BITS - 1 downto 0);
+    y: out std_logic_vector (BITS - 1 downto 0)
+  );
+end entity;
+architecture rtl of shift_register
+is
+  type signed_array is array (natural range <>) of signed;
+  signal shift_reg: signed_array (1 to NUM_STAGES - 1)(BITS - 1 downto 0);
+begin
+  process (clk, rst)
+  begin
+    if rst
+    then
+      shift_reg <= (others => (others => '0'));
+    elsif rising_edge (clk)
+    then
+      shift_reg <= signed (x) & shift_reg (1 to NUM_STAGES - 2);
+    end if;
+  end process;
+  y <= std_logic_vector (shift_reg (NUM_STAGES - 1));
+end architecture;
+
diff --git a/testsuite/gna/issue2407/shift_register_tb.vhdl b/testsuite/gna/issue2407/shift_register_tb.vhdl
new file mode 100644
index 000000000..9c1d9c875
--- /dev/null
+++ b/testsuite/gna/issue2407/shift_register_tb.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.env.finish;
+entity shift_register_tb is
+end shift_register_tb;
+architecture sim of shift_register_tb
+is
+  constant clk_hz: integer := 100e6;
+  constant clk_period: time := 1 sec / clk_hz;
+  -- number of stages
+  constant NUM_STAGES: natural := 5;
+  -- number of bits
+  constant BITS: natural := 4;
+  signal clk: std_logic := '1';
+  signal rst: std_logic := '1';
+  signal x: std_logic_vector (BITS - 1 downto 0) := (others => '0');
+  signal y: std_logic_vector (BITS - 1 downto 0);
+begin
+  clk <= not clk after clk_period / 2;
+  DUT: entity work.shift_register (rtl)
+    generic map (NUM_STAGES => NUM_STAGES, BITS => BITS)
+    port map (clk => clk, rst => rst, x => x, y => y);
+  SEQUENCER_PROC: process
+  begin
+    wait for clk_period * 2;
+    rst <= '0';
+    wait for clk_period;
+    for i in - 2** (BITS - 1) to 2** (BITS - 1) - 1 loop
+      x <= std_logic_vector (to_signed (i, BITS));
+      wait for clk_period;
+    end loop;
+    wait;
+  end process;
+  CHECK_PROC: process
+  begin
+    wait on rst;
+    wait for (NUM_STAGES + 1) * clk_period;
+    for i in - 2** (BITS - 1) to 2** (BITS - 1) - 1 loop
+      assert to_integer (signed (y)) = i report "y: " & to_string (to_integer (signed (y))) & " is not equal to " & to_string (i) severity failure;
+      wait for clk_period;
+    end loop;
+    wait for clk_period;
+    finish;
+  end process;
+end architecture;
+
diff --git a/testsuite/gna/issue2407/testsuite.sh b/testsuite/gna/issue2407/testsuite.sh
new file mode 100755
index 000000000..fe0f65add
--- /dev/null
+++ b/testsuite/gna/issue2407/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze shift_register.vhdl
+analyze shift_register_tb.vhdl
+elab_simulate shift_register_tb
+
+clean
+
+echo "Test successful"