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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-23 08:43:38 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-23 08:43:38 +0100 |
| commit | c121783be11334acd9226ef3962f5595c72e59d8 (patch) | |
| tree | b05dff87adbda6f71eabcb618bf3f32577fe38cd /testsuite | |
| parent | 536b6b43951f42ce3a7b80d58467ce816d6850d4 (diff) | |
| download | ghdl-c121783be11334acd9226ef3962f5595c72e59d8.tar.gz ghdl-c121783be11334acd9226ef3962f5595c72e59d8.tar.bz2 ghdl-c121783be11334acd9226ef3962f5595c72e59d8.zip | |
testsuite/synth: add tests for memory ports order.
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/synth/mem01/NOTES.txt | 3 | ||||
| -rw-r--r-- | testsuite/synth/mem01/sram03.vhdl | 29 | ||||
| -rwxr-xr-x | testsuite/synth/mem01/testsuite.sh | 2 |
3 files changed, 32 insertions, 2 deletions
diff --git a/testsuite/synth/mem01/NOTES.txt b/testsuite/synth/mem01/NOTES.txt index 3c362c073..8f8e1af0f 100644 --- a/testsuite/synth/mem01/NOTES.txt +++ b/testsuite/synth/mem01/NOTES.txt @@ -5,7 +5,8 @@ rom1: asynchronous ROM srom01: Read (initialized ROM). sram01: Read+Write (at the same address). -sram02: Write+Read (at the same address). +sram02: Write+Read (at the same address, enable, variable). +sram03: Read+Write (at the same address, enable, signal and R appears after W). dpram1: Read+Write (using signals, without enables) dpram2: Read+Write (using a variable, without enables) dpram3: Read+Write (like dpram2 but downto) diff --git a/testsuite/synth/mem01/sram03.vhdl b/testsuite/synth/mem01/sram03.vhdl new file mode 100644 index 000000000..01dfbd7d0 --- /dev/null +++ b/testsuite/synth/mem01/sram03.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sram03 is + port ( + clk_i : std_logic; + addr_i : std_logic_vector(3 downto 0); + data_i : std_logic_vector(7 downto 0); + data_o : out std_logic_vector(7 downto 0); + wen_i : std_logic); +end sram03; + +architecture behav of sram03 is + type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); + signal mem : mem_type; +begin + process (clk_i, addr_i) + variable addr : natural range mem_type'range; + begin + if rising_edge(clk_i) then + addr := to_integer (unsigned (addr_i)); + if wen_i = '1' then + mem (addr) <= data_i; + end if; + data_o <= mem (addr); + end if; + end process; +end behav; diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh index 073c69ea4..315ff4f4e 100755 --- a/testsuite/synth/mem01/testsuite.sh +++ b/testsuite/synth/mem01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in rom1 srom01 sram01 dpram1 dpram2 dpram3; do +for t in rom1 srom01 sram01 sram02 sram03 dpram1 dpram2 dpram3; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |