testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#110

2 files changed, 37 insertions, 0 deletions

diff --git a/testsuite/synth/synth110/testsuite.sh b/testsuite/synth/synth110/testsuite.sh
new file mode 100755
index 000000000..63190913e
--- /dev/null
+++ b/testsuite/synth/synth110/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze top
+grep "if rising_edge" syn_top.vhdl
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/synth/synth110/top.vhdl b/testsuite/synth/synth110/top.vhdl
new file mode 100644
index 000000000..aec306ea2
--- /dev/null
+++ b/testsuite/synth/synth110/top.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+    port(
+        clk  : in  std_logic;
+	di   : in  std_logic;
+        do   : out std_logic
+    ); 
+end top;
+
+architecture behavioral of top is
+    signal data : std_logic;
+begin
+
+    mylabel: process (clk)
+        variable tmp : std_logic;
+    begin
+        if rising_edge(clk) then
+            tmp := di;              -- Post-synthesis name : mylabel.tmp
+        end if;
+        data <= not(tmp);           
+    end process;
+
+    do <= not(data);
+    
+end behavioral;