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author | Tristan Gingold <tgingold@free.fr> | 2020-04-22 18:53:39 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-22 21:31:26 +0200 |
commit | e4efd609757cc9c303e3a27f421f5b75f551e5d2 (patch) | |
tree | a807876b394ea64db7808df019f1e2cd6a203a41 /testsuite | |
parent | b7992d8601cac632b75897182fb529c9409105ea (diff) | |
download | ghdl-e4efd609757cc9c303e3a27f421f5b75f551e5d2.tar.gz ghdl-e4efd609757cc9c303e3a27f421f5b75f551e5d2.tar.bz2 ghdl-e4efd609757cc9c303e3a27f421f5b75f551e5d2.zip |
testsuite/synth: add a test for #1254
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/issue1254/simple01.vhdl | 17 | ||||
-rw-r--r-- | testsuite/synth/issue1254/simple02.vhdl | 17 | ||||
-rwxr-xr-x | testsuite/synth/issue1254/testsuite.sh | 15 |
3 files changed, 49 insertions, 0 deletions
diff --git a/testsuite/synth/issue1254/simple01.vhdl b/testsuite/synth/issue1254/simple01.vhdl new file mode 100644 index 000000000..a0785240f --- /dev/null +++ b/testsuite/synth/issue1254/simple01.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity simple01 is + port (a : in std_logic; + z : out std_logic); +end simple01; + +--use work.pkg.all; + +architecture behav of simple01 is +begin + process(A) + begin + Z <= a; + end process; +end behav; diff --git a/testsuite/synth/issue1254/simple02.vhdl b/testsuite/synth/issue1254/simple02.vhdl new file mode 100644 index 000000000..01255409a --- /dev/null +++ b/testsuite/synth/issue1254/simple02.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity simple01 is + port (a : in std_logic; + z : out std_logic); +end simple01; + +--use work.pkg.all; + +architecture behav of simple01 is +begin + process(A) + begin + Z <= not a; + end process; +end behav; diff --git a/testsuite/synth/issue1254/testsuite.sh b/testsuite/synth/issue1254/testsuite.sh new file mode 100755 index 000000000..c12d2864e --- /dev/null +++ b/testsuite/synth/issue1254/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +cp simple01.vhdl simple.vhdl +analyze simple.vhdl + +cp simple02.vhdl simple.vhdl +if $GHDL --synth 2>&1 | grep "Bug occurred"; then + exit 1 +fi + +clean + +echo "Test successful" |