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authorTristan Gingold <tgingold@free.fr>2018-04-23 04:38:06 +0200
committerTristan Gingold <tgingold@free.fr>2018-04-23 04:38:06 +0200
commite501fff275b91610a202ce029cd3c0de416fa153 (patch)
treeb8da9166dc457f82736dfc3d7d0f11f4fd8a22dc /testsuite
parent90a760965427e064c50317f0609d6f6acc8b1def (diff)
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Add reproducer for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/bug088/assemble.vhdl37
-rwxr-xr-xtestsuite/gna/bug088/testsuite.sh9
2 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/gna/bug088/assemble.vhdl b/testsuite/gna/bug088/assemble.vhdl
new file mode 100644
index 000000000..e47c5b3dd
--- /dev/null
+++ b/testsuite/gna/bug088/assemble.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assemble is
+ port (
+ A: in std_logic_vector(31 downto 0);
+ B: in std_logic_vector(31 downto 0);
+ C: in std_logic_vector(31 downto 0);
+ F: out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture foo of assemble is
+
+ type std_logic_2d is array
+ (integer range <>, integer range <>) of std_logic;
+
+ signal data: std_logic_2d (31 downto 0, 2 downto 0);
+
+ function to_std_logic_2d (i0,i1,i2: std_logic_vector (31 downto 0))
+ return std_logic_2d is
+ variable retdat: std_logic_2d (data'range(0), data'range(1));
+ begin
+ for i in i0'range loop
+ retdat(i, 0) := i0(i);
+ retdat(i, 1) := i1(i);
+ retdat(i, 2) := i2(i);
+ end loop;
+ return retdat;
+ end function;
+
+begin
+
+ data <= to_std_logic_2d(A, B, C);
+ F <= (others => data (15, 1)); -- B(15)
+
+ end architecture;
diff --git a/testsuite/gna/bug088/testsuite.sh b/testsuite/gna/bug088/testsuite.sh
new file mode 100755
index 000000000..8d75b885c
--- /dev/null
+++ b/testsuite/gna/bug088/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure assemble.vhdl
+
+clean
+
+echo "Test successful"