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author | Tristan Gingold <tgingold@free.fr> | 2018-02-03 14:53:53 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-02-03 14:53:53 +0100 |
commit | e871dd0790360e4a88bd8337047aa93593be64e4 (patch) | |
tree | edae4771f35cb9de685339144e69665ce16dd923 /testsuite | |
parent | 2f647d9fd9d6f15dfaf2d9a8971f8e3f36563b60 (diff) | |
download | ghdl-e871dd0790360e4a88bd8337047aa93593be64e4.tar.gz ghdl-e871dd0790360e4a88bd8337047aa93593be64e4.tar.bz2 ghdl-e871dd0790360e4a88bd8337047aa93593be64e4.zip |
Add testcase for #524
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/issue524/cond.vhdl | 21 | ||||
-rw-r--r-- | testsuite/gna/issue524/cond2.vhdl | 23 | ||||
-rw-r--r-- | testsuite/gna/issue524/spi2apb.vhdl | 70 | ||||
-rwxr-xr-x | testsuite/gna/issue524/testsuite.sh | 12 |
4 files changed, 126 insertions, 0 deletions
diff --git a/testsuite/gna/issue524/cond.vhdl b/testsuite/gna/issue524/cond.vhdl new file mode 100644 index 000000000..5954b1e6c --- /dev/null +++ b/testsuite/gna/issue524/cond.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cond is + port (i, rst, clk : std_logic; + o : out std_logic); +end; + +architecture behav of cond is +begin + process (clk) is + begin + if rising_edge(clk) then + if rst then + o <= '0'; + else + o <= i; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue524/cond2.vhdl b/testsuite/gna/issue524/cond2.vhdl new file mode 100644 index 000000000..c109258c5 --- /dev/null +++ b/testsuite/gna/issue524/cond2.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +entity cond is + port (i, rst, clk: std_logic; + o: out std_logic); +end; + + +architecture behav of cond is +begin + process (clk) is + begin + if rising_edge(clk) then + if ?? rst then + o <= '0'; + else + o <= i; + end if; + end if; + end process; +end; + + diff --git a/testsuite/gna/issue524/spi2apb.vhdl b/testsuite/gna/issue524/spi2apb.vhdl new file mode 100644 index 000000000..4dc124793 --- /dev/null +++ b/testsuite/gna/issue524/spi2apb.vhdl @@ -0,0 +1,70 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity spi2apb is + port ( + -- SPI + signal MISO : in std_logic; + signal MOSI : out std_logic; + signal SCLK : out std_logic; + signal SS_n : out std_logic; + + -- APB + signal apb_select : in std_logic; + signal clk : in std_logic; + signal data_in : in std_logic_vector (15 downto 0); + signal data_out : out std_logic_vector (15 downto 0); + signal addr : in std_logic_vector (2 downto 0); + signal read_n : in std_logic; + signal reset_n : in std_logic; + signal write_n : in std_logic +); +end entity spi2apb; + +architecture rtl of spi2apb is + type reg_type is record + enabled: std_logic; + sclk: std_logic; + running: std_logic; + continuous: std_logic; + pending: std_logic; + txValid, rxValid: std_logic; + txBuffer, rxBuffer, shift: std_logic_vector(7 downto 0); + end record; + + constant reg_reset: reg_type := ( + enabled => '0', + sclk => '0', + running => '0', + continuous => '0', + pending => '0', + txValid => '0', + rxValid => '0', + txBuffer => (others => '0'), + shift => (others => '0'), + rxBuffer => (others => '0') + ); + + signal reg_in, reg_out: reg_type; +begin + MOSI <= reg_out.shift(7); + SCLK <= reg_out.sclk; + SS_n <= not reg_out.enabled; + data_out <= "000000" & (reg_out.running or reg_out.pending) & reg_out.rxValid & reg_out.rxBuffer; + + sync: process(clk, reset_n) + begin + if (rising_edge(clk)) then + reg_in <= reg_reset when (reset_n => '0') else reg_out; + end if; + end process; + + clocking: process(reg_in) + begin + if (reg_in.running) then + reg_out.sclk <= "0" when reg_in else "1"; + end if; + end process; +end; + +-- vim: set sw=3 ts=3 sts=3 et sta sr ai si cin cino=>1s(0u0W1s: diff --git a/testsuite/gna/issue524/testsuite.sh b/testsuite/gna/issue524/testsuite.sh new file mode 100755 index 000000000..070121d39 --- /dev/null +++ b/testsuite/gna/issue524/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure spi2apb.vhdl + +analyze cond.vhdl + +clean + +echo "Test successful" |