Add testcase for #450

4 files changed, 196 insertions, 0 deletions

diff --git a/testsuite/gna/issue450/disptree.ref b/testsuite/gna/issue450/disptree.ref
new file mode 100644
index 000000000..97ec2f6b4
--- /dev/null
+++ b/testsuite/gna/issue450/disptree.ref
@@ -0,0 +1,19 @@
+elaborate and simulate disptree --vpi=./vpi2.vpi
+got to here 
+got to here1 
+Module disptree:
+Full module name (vpiFullName): 	disptree
+Simple module name (vpiName): 		disptree
+ net clk
+ net a
+ net b
+Full module name (vpiFullName): 	disptree.gen_for(1)
+Simple module name (vpiName): 		gen_for(1)
+Full module name (vpiFullName): 	disptree.gen_for(2)
+Simple module name (vpiName): 		gen_for(2)
+Full module name (vpiFullName): 	disptree.gen_for(3)
+Simple module name (vpiName): 		gen_for(3)
+Full module name (vpiFullName): 	disptree.gen_for(4)
+Simple module name (vpiName): 		gen_for(4)
+Full module name (vpiFullName): 	disptree.gen_if
+Simple module name (vpiName): 		B1
diff --git a/testsuite/gna/issue450/disptree.vhdl b/testsuite/gna/issue450/disptree.vhdl
new file mode 100644
index 000000000..11f9d87ea
--- /dev/null
+++ b/testsuite/gna/issue450/disptree.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity disptree is
+    port ( 
+        clk : in std_logic;
+        A : in std_logic_vector(5 downto 1);
+        B : out std_logic_vector(5 downto 1)
+    );
+end disptree;
+
+architecture rtl of disptree is
+begin
+    gen_for : for i in 1 to 4 generate
+        test1: process (clk) is
+        begin
+            if (rising_edge(clk)) then 
+                B(i) <= A(i);
+            end if;
+        end process test1;
+    end generate gen_for;
+    
+    gen_if : if True generate
+		test2: process (clk) is
+        begin
+            if (rising_edge(clk)) then 
+                B(5) <= A(5);
+            end if;
+        end process test2;
+	end generate gen_if;
+end rtl;
+
diff --git a/testsuite/gna/issue450/testsuite.sh b/testsuite/gna/issue450/testsuite.sh
new file mode 100755
index 000000000..31ada14d0
--- /dev/null
+++ b/testsuite/gna/issue450/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+$GHDL --vpi-compile -v gcc -c vpi2.c
+$GHDL --vpi-link -v gcc -o vpi2.vpi vpi2.o
+
+analyze disptree.vhdl
+elab_simulate disptree --vpi=./vpi2.vpi | tee disptree.out
+diff --strip-trailing-cr -q disptree.ref disptree.out
+
+rm -f vpi2.o vpi2.vpi disptree.out
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue450/vpi2.c b/testsuite/gna/issue450/vpi2.c
new file mode 100644
index 000000000..0debb546b
--- /dev/null
+++ b/testsuite/gna/issue450/vpi2.c
@@ -0,0 +1,129 @@
+/*****************************************************************************
+
+ * Test vpi program
+ * vpi handle  File = printNets.c
+
+*****************************************************************************/
+
+#include <stdio.h>
+#include <vpi_user.h>
+
+/*****************************************************************************
+ * User program
+ * my handle
+ *****************************************************************************/
+
+void printContent (vpiHandle parent)
+{
+  vpiHandle Iterator;
+
+  vpi_printf ("Full module name (vpiFullName): \t%s\n", vpi_get_str (vpiFullName, parent));
+  vpi_printf ("Simple module name (vpiName): \t\t%s\n", vpi_get_str (vpiName, parent));
+
+  Iterator = vpi_iterate (vpiNet, parent);
+  if (Iterator)
+    {
+      vpiHandle netHandle;
+      while ((netHandle = vpi_scan (Iterator)))
+	{
+	  char *NetName = vpi_get_str (vpiName, netHandle);
+	  vpi_printf (" net %s\n", NetName);
+	}
+    }
+
+  Iterator = vpi_iterate (vpiModule, parent);
+  if (Iterator)
+    {
+      vpiHandle scopeHandle;
+      while ((scopeHandle = vpi_scan (Iterator)))
+	printContent (scopeHandle);
+    }
+}
+
+void printModules()
+{
+  vpiHandle topModIterator;
+  vpiHandle topModHandle;
+  
+  char *ModName;
+
+  vpi_printf ("got to here \n");
+  /* create a module iterator that starts at the top  as indicated by NULL */
+  topModIterator = vpi_iterate (vpiModule, NULL);
+  vpi_printf ("got to here1 \n");
+  if (!topModIterator)
+    {
+      return;
+    }
+
+  /* use vpi_scan to iterate throught modules */
+  while ((topModHandle = vpi_scan (topModIterator)))
+    {
+      ModName = vpi_get_str (vpiName, topModHandle);
+      vpi_printf ("Module %s:\n", ModName);
+
+      printContent (topModHandle);
+    }
+}
+
+
+/*****************************************************************************
+ * Creating  structure
+ *****************************************************************************/
+
+void my_handle_register()
+{
+#if 0
+  s_vpi_systf_data tf_data;
+
+  tf_data.type      = vpiSysTask;
+  tf_data.tfname    = "$printNets";
+  tf_data.calltf    = printModules;
+  tf_data.compiletf = 0;
+  tf_data.sizetf    = 0;
+  vpi_register_systf(&tf_data);
+#else
+  s_cb_data cb;
+
+  cb.reason = cbEndOfCompile;
+  cb.cb_rtn = &printModules;
+  cb.user_data = NULL;
+  if (vpi_register_cb (&cb) == NULL)
+    vpi_printf ("cannot register EndOfCompile call back\n");
+#endif
+}
+// register the  task
+
+void (*vlog_startup_routines[]) () =
+{
+  my_handle_register,
+  0
+};
+
+/*  Makefile:
+#############################
+
+##Sample make file to compile a vpi routine with iverilog
+CC = gcc
+OBJECTS = printNets.o
+DLL = printNets.vpi
+CFLAG = -0
+
+#compile all the objects
+.c.o:;
+ $(CC) -c -g -o   $@ $<
+
+all: $(DLL) graycntr.v
+ iverilog -N graycntr.v -o graycntr -m ./printNets.vpi
+
+$(DLL): $(OBJECTS)
+ $(CC) -o $(DLL) -shared $(OBJECTS) -lvpi
+
+clean :
+ rm -rf *.o
+ rm -rf *.vpi
+ rm -rf *~
+ rm -rf core
+*/
+
+