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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-19 03:20:59 +0200 |
|---|---|---|
| committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-19 15:25:07 +0200 |
| commit | ef0dbc726749df434036b23480b89f01cbe67d44 (patch) | |
| tree | b7573b77a0662773ffe30b100d7537de3d56f21a /testsuite | |
| parent | 89f835733c4019c5cb087885a874f34cf4ff183d (diff) | |
| download | ghdl-ef0dbc726749df434036b23480b89f01cbe67d44.tar.gz ghdl-ef0dbc726749df434036b23480b89f01cbe67d44.tar.bz2 ghdl-ef0dbc726749df434036b23480b89f01cbe67d44.zip | |
Added handling of Parenthesis.
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/pyunit/SimpleEntity.vhdl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl index 90d68fd83..931599086 100644 --- a/testsuite/pyunit/SimpleEntity.vhdl +++ b/testsuite/pyunit/SimpleEntity.vhdl @@ -4,7 +4,7 @@ use ieee.numeric_std.all; entity entity_1 is generic ( - FREQ : real := 100.0; + FREQ : real := (100.0 * 1024.0 * 1024.0); BITS : positive := 8 ); port ( @@ -17,7 +17,7 @@ end entity entity_1; architecture behav of entity_1 is signal Reset_n : std_logic; begin - Reset_n <= not Reset; + Reset_n <= (not Reset); process(Clock) begin |