testsuite/synth: add asgn01

5 files changed, 124 insertions, 0 deletions

diff --git a/testsuite/synth/asgn01/arr04.vhdl b/testsuite/synth/asgn01/arr04.vhdl
new file mode 100644
index 000000000..9f0d2fd1f
--- /dev/null
+++ b/testsuite/synth/asgn01/arr04.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity arr04 is
+  port (clk : in std_logic;
+        rst : std_logic;
+        sel_i : std_logic;
+        v : std_logic;
+        res : out std_logic_vector(0 to 1));
+end arr04;
+
+architecture behav of arr04 is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        res <= "00";
+      else
+        if sel_i = '0' then
+          res (0) <= v;
+        else
+          res (1) <= v;
+        end if;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/asgn01.vhdl b/testsuite/synth/asgn01/asgn01.vhdl
new file mode 100644
index 000000000..731aaa207
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn01.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn01 is
+  port (a : std_logic_vector (2 downto 0);
+        s0 : std_logic;
+        r : out std_logic_vector (2 downto 0));
+end asgn01;
+
+architecture behav of asgn01 is
+begin
+  process (a, s0) is
+  begin
+    if s0 = '1' then
+      r <= "000";
+    else
+      r <= a;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/asgn02.vhdl b/testsuite/synth/asgn01/asgn02.vhdl
new file mode 100644
index 000000000..f83690d8b
--- /dev/null
+++ b/testsuite/synth/asgn01/asgn02.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn02 is
+  port (a : std_logic_vector (2 downto 0);
+        s0 : std_logic;
+        r : out std_logic_vector (2 downto 0));
+end asgn02;
+
+architecture behav of asgn02 is
+begin
+  process (a, s0) is
+  begin
+    r <= "000";
+    if s0 = '1' then
+      r (1) <= '1';
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/tb_arr04.vhdl b/testsuite/synth/asgn01/tb_arr04.vhdl
new file mode 100644
index 000000000..175650af7
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_arr04.vhdl
@@ -0,0 +1,41 @@
+entity tb_arr04 is
+end tb_arr04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_arr04 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal sel_i : std_logic;
+  signal v : std_logic;
+  signal r : std_logic_vector(0 to 1);
+begin
+  dut: entity work.arr04
+    port map (clk => clk, rst => rst, sel_i => sel_i, v => v, res => r);
+
+  process
+    constant siv : std_logic_vector := b"0010";
+    constant v_v : std_logic_vector := b"0011";
+    constant r1v : std_logic_vector := b"0011";
+    constant r0v : std_logic_vector := b"0001";
+  begin
+    clk <= '0';
+    rst <= '1';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+    rst <= '0';
+    for i in siv'range loop
+      sel_i <= siv (i);
+      v <= v_v (i);
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+      assert r(0) = r0v(i) severity failure;
+      assert r(1) = r1v(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/asgn01/testsuite.sh b/testsuite/synth/asgn01/testsuite.sh
new file mode 100755
index 000000000..8595e02ab
--- /dev/null
+++ b/testsuite/synth/asgn01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in arr04; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"