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authorTristan Gingold <tgingold@free.fr>2018-10-18 06:29:48 +0200
committerTristan Gingold <tgingold@free.fr>2018-10-21 08:03:37 +0200
commitf910e02797a83d0c5748768d20359a3d95569cc7 (patch)
treeb979d295d880af3cf10f54e9fd2708e07d5e1ec6 /testsuite
parentffa1a498dc22b7758d096cd91c61f0d356879e47 (diff)
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Add testcase for #668
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/issue668/repro2.vhdl40
-rw-r--r--testsuite/gna/issue668/tb.vhdl54
-rwxr-xr-xtestsuite/gna/issue668/testsuite.sh25
3 files changed, 119 insertions, 0 deletions
diff --git a/testsuite/gna/issue668/repro2.vhdl b/testsuite/gna/issue668/repro2.vhdl
new file mode 100644
index 000000000..255f72835
--- /dev/null
+++ b/testsuite/gna/issue668/repro2.vhdl
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package wishbone_pkg2 is
+ subtype my_vector is std_logic_vector;
+
+ type t_wishbone_master_out is record
+ dat : my_vector;
+ end record;
+ subtype t_wishbone_slave_in is t_wishbone_master_out;
+end wishbone_pkg2;
+
+library work;
+use work.wishbone_pkg2.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+end entity;
+architecture bench of repro2 is
+ signal wbs_s : t_wishbone_slave_in(
+ dat(32-1 downto 0)
+ );
+begin
+ stimulus : process
+ begin
+ wbs_s.dat <= x"deadbeef";
+ wait for 100 ns;
+ report "pass" severity note;
+ wait;
+ end process;
+
+ dut : block
+ port (wbs_i : in t_wishbone_slave_in);
+ port map (wbs_i => wbs_s);
+ begin
+ end block;
+end architecture;
+
diff --git a/testsuite/gna/issue668/tb.vhdl b/testsuite/gna/issue668/tb.vhdl
new file mode 100644
index 000000000..768038201
--- /dev/null
+++ b/testsuite/gna/issue668/tb.vhdl
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package wishbone_pkg is
+--./wb_demux_tb:internal error: wave.create_type
+ type t_wishbone_master_out is record
+ dat : std_logic_vector;
+ end record;
+ subtype t_wishbone_slave_in is t_wishbone_master_out;
+end wishbone_pkg;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity wb_demux is
+ Port (
+ wbs_i : in t_wishbone_slave_in
+ );
+end wb_demux;
+architecture full_regs of wb_demux is
+begin
+end full_regs;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity wb_demux_tb is
+end entity;
+architecture bench of wb_demux_tb is
+ signal wbs_i : t_wishbone_slave_in(
+ dat(32-1 downto 0)
+ );
+begin
+ stimulus : process
+ begin
+ wbs_i.dat <= x"deadbeef";
+ wait for 100 ns;
+ report "pass" severity note;
+ wait;
+ end process;
+
+ dut : entity work.wb_demux
+ port map (
+ wbs_i => wbs_i
+ );
+end architecture;
+
diff --git a/testsuite/gna/issue668/testsuite.sh b/testsuite/gna/issue668/testsuite.sh
new file mode 100755
index 000000000..19b6004b5
--- /dev/null
+++ b/testsuite/gna/issue668/testsuite.sh
@@ -0,0 +1,25 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze tb.vhdl
+elab wb_demux_tb
+
+if ghdl_has_feature wb_demux_tb ghw; then
+ simulate wb_demux_tb --dump-rti
+ simulate wb_demux_tb --wave=w.ghw
+fi
+
+analyze repro2.vhdl
+elab repro2
+if ghdl_has_feature repro2 ghw; then
+ simulate repro2 --dump-rti
+ simulate repro2 --wave=w.ghw
+fi
+
+clean
+
+rm -f w.ghw
+
+echo "Test successful"