testsuite/synth: add a test for false latch

2 files changed, 28 insertions, 0 deletions

diff --git a/testsuite/synth/case01/case05.vhdl b/testsuite/synth/case01/case05.vhdl
new file mode 100644
index 000000000..82f6ff5cf
--- /dev/null
+++ b/testsuite/synth/case01/case05.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case05 is
+    port (
+	in_en  : std_logic;
+	in_v  : std_logic_vector(3 downto 0)
+	);
+end entity case05;
+
+architecture behav of case05 is
+begin
+    process(in_en, in_v)
+	variable l : boolean;
+    begin
+	if in_en = '1' then
+	    case in_v is
+
+	    when "0010" =>
+		l := in_v = "0000";
+	    when others =>
+		report "illegal";
+	    end case;
+	end if;
+    end process;
+end architecture behav;
diff --git a/testsuite/synth/case01/testsuite.sh b/testsuite/synth/case01/testsuite.sh
index 8ff30eaf1..519aaff89 100755
--- a/testsuite/synth/case01/testsuite.sh
+++ b/testsuite/synth/case01/testsuite.sh
@@ -6,4 +6,6 @@ for t in case01 case02 case03 case04; do
     synth_tb $t
 done
 
+synth case05.vhdl -e case05 > syn_case05.vhdl
+
 echo "Test successful"