diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 186 | ||||
| -rw-r--r-- | src/std_names.adb | 2 | ||||
| -rw-r--r-- | src/std_names.ads | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 10 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 |
5 files changed, 112 insertions, 93 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 67ed3088d..e0f7425ec 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1425,98 +1425,100 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Conv_Vector_Uns = 442 Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 443 Ieee_Std_Logic_Arith_Conv_Vector_Log = 444 - Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 445 - Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 446 - Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 447 - Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 448 - Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 449 - Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 450 - Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 451 - Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 452 - Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 453 - Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 454 - Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 455 - Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 456 - Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 457 - Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 458 - Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 459 - Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 460 - Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 461 - Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 462 - Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 463 - Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 464 - Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 465 - Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 466 - Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 467 - Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 468 - Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 469 - Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 470 - Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 471 - Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 472 - Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 473 - Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 474 - Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 475 - Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 476 - Ieee_Std_Logic_Arith_Lt_Uns_Uns = 477 - Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 478 - Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 479 - Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 480 - Ieee_Std_Logic_Arith_Lt_Uns_Int = 481 - Ieee_Std_Logic_Arith_Lt_Int_Uns = 482 - Ieee_Std_Logic_Arith_Lt_Sgn_Int = 483 - Ieee_Std_Logic_Arith_Lt_Int_Sgn = 484 - Ieee_Std_Logic_Arith_Le_Uns_Uns = 485 - Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 486 - Ieee_Std_Logic_Arith_Le_Uns_Sgn = 487 - Ieee_Std_Logic_Arith_Le_Sgn_Uns = 488 - Ieee_Std_Logic_Arith_Le_Uns_Int = 489 - Ieee_Std_Logic_Arith_Le_Int_Uns = 490 - Ieee_Std_Logic_Arith_Le_Sgn_Int = 491 - Ieee_Std_Logic_Arith_Le_Int_Sgn = 492 - Ieee_Std_Logic_Arith_Gt_Uns_Uns = 493 - Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 494 - Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 495 - Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 496 - Ieee_Std_Logic_Arith_Gt_Uns_Int = 497 - Ieee_Std_Logic_Arith_Gt_Int_Uns = 498 - Ieee_Std_Logic_Arith_Gt_Sgn_Int = 499 - Ieee_Std_Logic_Arith_Gt_Int_Sgn = 500 - Ieee_Std_Logic_Arith_Ge_Uns_Uns = 501 - Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 502 - Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 503 - Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 504 - Ieee_Std_Logic_Arith_Ge_Uns_Int = 505 - Ieee_Std_Logic_Arith_Ge_Int_Uns = 506 - Ieee_Std_Logic_Arith_Ge_Sgn_Int = 507 - Ieee_Std_Logic_Arith_Ge_Int_Sgn = 508 - Ieee_Std_Logic_Arith_Eq_Uns_Uns = 509 - Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 510 - Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 511 - Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 512 - Ieee_Std_Logic_Arith_Eq_Uns_Int = 513 - Ieee_Std_Logic_Arith_Eq_Int_Uns = 514 - Ieee_Std_Logic_Arith_Eq_Sgn_Int = 515 - Ieee_Std_Logic_Arith_Eq_Int_Sgn = 516 - Ieee_Std_Logic_Arith_Ne_Uns_Uns = 517 - Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 518 - Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 519 - Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 520 - Ieee_Std_Logic_Arith_Ne_Uns_Int = 521 - Ieee_Std_Logic_Arith_Ne_Int_Uns = 522 - Ieee_Std_Logic_Arith_Ne_Sgn_Int = 523 - Ieee_Std_Logic_Arith_Ne_Int_Sgn = 524 - Ieee_Std_Logic_Misc_And_Reduce_Slv = 525 - Ieee_Std_Logic_Misc_And_Reduce_Suv = 526 - Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 527 - Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 528 - Ieee_Std_Logic_Misc_Or_Reduce_Slv = 529 - Ieee_Std_Logic_Misc_Or_Reduce_Suv = 530 - Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 531 - Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 532 - Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 533 - Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 534 - Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 535 - Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 536 + Ieee_Std_Logic_Arith_Ext = 445 + Ieee_Std_Logic_Arith_Sxt = 446 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 447 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 448 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 449 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 450 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 451 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 452 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 453 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 454 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 455 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 456 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 457 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 458 + Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 459 + Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 460 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 461 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 462 + Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 463 + Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 464 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 465 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 466 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 467 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 468 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 469 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 470 + Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 471 + Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 472 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 473 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 474 + Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 475 + Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 476 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 477 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 478 + Ieee_Std_Logic_Arith_Lt_Uns_Uns = 479 + Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 480 + Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 481 + Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 482 + Ieee_Std_Logic_Arith_Lt_Uns_Int = 483 + Ieee_Std_Logic_Arith_Lt_Int_Uns = 484 + Ieee_Std_Logic_Arith_Lt_Sgn_Int = 485 + Ieee_Std_Logic_Arith_Lt_Int_Sgn = 486 + Ieee_Std_Logic_Arith_Le_Uns_Uns = 487 + Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 488 + Ieee_Std_Logic_Arith_Le_Uns_Sgn = 489 + Ieee_Std_Logic_Arith_Le_Sgn_Uns = 490 + Ieee_Std_Logic_Arith_Le_Uns_Int = 491 + Ieee_Std_Logic_Arith_Le_Int_Uns = 492 + Ieee_Std_Logic_Arith_Le_Sgn_Int = 493 + Ieee_Std_Logic_Arith_Le_Int_Sgn = 494 + Ieee_Std_Logic_Arith_Gt_Uns_Uns = 495 + Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 496 + Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 497 + Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 498 + Ieee_Std_Logic_Arith_Gt_Uns_Int = 499 + Ieee_Std_Logic_Arith_Gt_Int_Uns = 500 + Ieee_Std_Logic_Arith_Gt_Sgn_Int = 501 + Ieee_Std_Logic_Arith_Gt_Int_Sgn = 502 + Ieee_Std_Logic_Arith_Ge_Uns_Uns = 503 + Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 504 + Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 505 + Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 506 + Ieee_Std_Logic_Arith_Ge_Uns_Int = 507 + Ieee_Std_Logic_Arith_Ge_Int_Uns = 508 + Ieee_Std_Logic_Arith_Ge_Sgn_Int = 509 + Ieee_Std_Logic_Arith_Ge_Int_Sgn = 510 + Ieee_Std_Logic_Arith_Eq_Uns_Uns = 511 + Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 512 + Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 513 + Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 514 + Ieee_Std_Logic_Arith_Eq_Uns_Int = 515 + Ieee_Std_Logic_Arith_Eq_Int_Uns = 516 + Ieee_Std_Logic_Arith_Eq_Sgn_Int = 517 + Ieee_Std_Logic_Arith_Eq_Int_Sgn = 518 + Ieee_Std_Logic_Arith_Ne_Uns_Uns = 519 + Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 520 + Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 521 + Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 522 + Ieee_Std_Logic_Arith_Ne_Uns_Int = 523 + Ieee_Std_Logic_Arith_Ne_Int_Uns = 524 + Ieee_Std_Logic_Arith_Ne_Sgn_Int = 525 + Ieee_Std_Logic_Arith_Ne_Int_Sgn = 526 + Ieee_Std_Logic_Misc_And_Reduce_Slv = 527 + Ieee_Std_Logic_Misc_And_Reduce_Suv = 528 + Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 529 + Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 530 + Ieee_Std_Logic_Misc_Or_Reduce_Slv = 531 + Ieee_Std_Logic_Misc_Or_Reduce_Suv = 532 + Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 533 + Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 534 + Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 535 + Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 536 + Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 537 + Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 538 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index 9d9cfcbe7..ece86763f 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -668,6 +668,8 @@ package body Std_Names is Def ("log2", Name_Log2); Def ("sin", Name_Sin); Def ("cos", Name_Cos); + Def ("ext", Name_Ext); + Def ("sxt", Name_Sxt); Def ("allconst", Name_Allconst); Def ("allseq", Name_Allseq); diff --git a/src/std_names.ads b/src/std_names.ads index 2c12c0f00..6ed7fb6d5 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -751,7 +751,9 @@ package Std_Names is Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 038; Name_Sin : constant Name_Id := Name_First_Ieee_Name + 039; Name_Cos : constant Name_Id := Name_First_Ieee_Name + 040; - Name_Last_Ieee_Name : constant Name_Id := Name_Cos; + Name_Ext : constant Name_Id := Name_First_Ieee_Name + 041; + Name_Sxt : constant Name_Id := Name_First_Ieee_Name + 042; + Name_Last_Ieee_Name : constant Name_Id := Name_Sxt; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; Name_Allconst : constant Name_Id := Name_First_Synthesis + 000; diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index 4c2b517ec..c1d7caccf 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -397,6 +397,16 @@ package body Vhdl.Ieee.Std_Logic_Arith is Def := Handle_Cmp (Eq_Patterns); when Name_Op_Inequality => Def := Handle_Cmp (Ne_Patterns); + when Name_Ext => + if Arg1_Kind /= Type_Slv or Arg2_Kind /= Type_Int then + raise Error; + end if; + Def := Iir_Predefined_Ieee_Std_Logic_Arith_Ext; + when Name_Sxt => + if Arg1_Kind /= Type_Slv or Arg2_Kind /= Type_Int then + raise Error; + end if; + Def := Iir_Predefined_Ieee_Std_Logic_Arith_Sxt; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c6f7d0891..393780a3f 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5782,6 +5782,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log, + Iir_Predefined_Ieee_Std_Logic_Arith_Ext, + Iir_Predefined_Ieee_Std_Logic_Arith_Sxt, + Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn, |