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-rw-r--r--testsuite/synth/issue1079/test.vhdl41
-rwxr-xr-xtestsuite/synth/issue1079/testsuite.sh7
2 files changed, 48 insertions, 0 deletions
diff --git a/testsuite/synth/issue1079/test.vhdl b/testsuite/synth/issue1079/test.vhdl
new file mode 100644
index 000000000..48d1e68e9
--- /dev/null
+++ b/testsuite/synth/issue1079/test.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+ port(
+ clk : in std_logic;
+
+ rd_en : in std_logic;
+ rd_addr : in std_logic_vector(15 downto 0);
+ rd_data : out std_logic_vector(63 downto 0);
+
+ wr_en : in std_logic;
+ wr_sel : in std_logic_vector(7 downto 0);
+ wr_addr : in std_logic_vector(15 downto 0);
+ wr_data : in std_logic_vector(63 downto 0)
+ );
+end test;
+
+architecture rtl of test is
+ constant SIZE : integer := 2**16;
+ type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0);
+ signal ram : ram_type;
+ signal rd_data0 : std_logic_vector(63 downto 0);
+begin
+ process(clk)
+ variable widx : integer range 0 to SIZE - 1;
+ begin
+ if rising_edge(clk) then
+ if wr_en = '1' then
+ widx := to_integer(unsigned(wr_addr));
+ ram(widx) <= wr_data;
+ end if;
+ if rd_en = '1' then
+ rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+ end if;
+ end if;
+ end process;
+
+ rd_data <= rd_data0;
+end;
diff --git a/testsuite/synth/issue1079/testsuite.sh b/testsuite/synth/issue1079/testsuite.sh
new file mode 100755
index 000000000..96710f416
--- /dev/null
+++ b/testsuite/synth/issue1079/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=raw test.vhdl -e | grep -q mem_rd_sync
+
+echo "Test successful"