diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 176 | ||||
| -rw-r--r-- | src/vhdl/vhdl-canon.adb | 27 | ||||
| -rw-r--r-- | src/vhdl/vhdl-elocations.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-elocations.ads | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-elocations_meta.adb | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-errors.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 39 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_meta.adb | 210 | ||||
| -rw-r--r-- | src/vhdl/vhdl-parse.adb | 154 | ||||
| -rw-r--r-- | src/vhdl/vhdl-prints.adb | 129 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_stmts.adb | 34 |
12 files changed, 539 insertions, 241 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index dce74a709..c03729f69 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -227,92 +227,94 @@ class Iir_Kind: Generate_Statement_Body = 212 If_Generate_Else_Clause = 213 Simple_Simultaneous_Statement = 214 - Simultaneous_Procedural_Statement = 215 - Simultaneous_If_Statement = 216 - Simultaneous_Elsif = 217 - Simple_Signal_Assignment_Statement = 218 - Conditional_Signal_Assignment_Statement = 219 - Selected_Waveform_Assignment_Statement = 220 - Null_Statement = 221 - Assertion_Statement = 222 - Report_Statement = 223 - Wait_Statement = 224 - Variable_Assignment_Statement = 225 - Conditional_Variable_Assignment_Statement = 226 - Return_Statement = 227 - For_Loop_Statement = 228 - While_Loop_Statement = 229 - Next_Statement = 230 - Exit_Statement = 231 - Case_Statement = 232 - Procedure_Call_Statement = 233 - Break_Statement = 234 - If_Statement = 235 - Elsif = 236 - Character_Literal = 237 - Simple_Name = 238 - Selected_Name = 239 - Operator_Symbol = 240 - Reference_Name = 241 - External_Constant_Name = 242 - External_Signal_Name = 243 - External_Variable_Name = 244 - Selected_By_All_Name = 245 - Parenthesis_Name = 246 - Package_Pathname = 247 - Absolute_Pathname = 248 - Relative_Pathname = 249 - Pathname_Element = 250 - Base_Attribute = 251 - Subtype_Attribute = 252 - Element_Attribute = 253 - Across_Attribute = 254 - Through_Attribute = 255 - Nature_Reference_Attribute = 256 - Left_Type_Attribute = 257 - Right_Type_Attribute = 258 - High_Type_Attribute = 259 - Low_Type_Attribute = 260 - Ascending_Type_Attribute = 261 - Image_Attribute = 262 - Value_Attribute = 263 - Pos_Attribute = 264 - Val_Attribute = 265 - Succ_Attribute = 266 - Pred_Attribute = 267 - Leftof_Attribute = 268 - Rightof_Attribute = 269 - Signal_Slew_Attribute = 270 - Quantity_Slew_Attribute = 271 - Ramp_Attribute = 272 - Dot_Attribute = 273 - Integ_Attribute = 274 - Above_Attribute = 275 - Delayed_Attribute = 276 - Stable_Attribute = 277 - Quiet_Attribute = 278 - Transaction_Attribute = 279 - Event_Attribute = 280 - Active_Attribute = 281 - Last_Event_Attribute = 282 - Last_Active_Attribute = 283 - Last_Value_Attribute = 284 - Driving_Attribute = 285 - Driving_Value_Attribute = 286 - Behavior_Attribute = 287 - Structure_Attribute = 288 - Simple_Name_Attribute = 289 - Instance_Name_Attribute = 290 - Path_Name_Attribute = 291 - Left_Array_Attribute = 292 - Right_Array_Attribute = 293 - High_Array_Attribute = 294 - Low_Array_Attribute = 295 - Length_Array_Attribute = 296 - Ascending_Array_Attribute = 297 - Range_Array_Attribute = 298 - Reverse_Range_Array_Attribute = 299 - Attribute_Name = 300 + Simultaneous_Null_Statement = 215 + Simultaneous_Procedural_Statement = 216 + Simultaneous_Case_Statement = 217 + Simultaneous_If_Statement = 218 + Simultaneous_Elsif = 219 + Simple_Signal_Assignment_Statement = 220 + Conditional_Signal_Assignment_Statement = 221 + Selected_Waveform_Assignment_Statement = 222 + Null_Statement = 223 + Assertion_Statement = 224 + Report_Statement = 225 + Wait_Statement = 226 + Variable_Assignment_Statement = 227 + Conditional_Variable_Assignment_Statement = 228 + Return_Statement = 229 + For_Loop_Statement = 230 + While_Loop_Statement = 231 + Next_Statement = 232 + Exit_Statement = 233 + Case_Statement = 234 + Procedure_Call_Statement = 235 + Break_Statement = 236 + If_Statement = 237 + Elsif = 238 + Character_Literal = 239 + Simple_Name = 240 + Selected_Name = 241 + Operator_Symbol = 242 + Reference_Name = 243 + External_Constant_Name = 244 + External_Signal_Name = 245 + External_Variable_Name = 246 + Selected_By_All_Name = 247 + Parenthesis_Name = 248 + Package_Pathname = 249 + Absolute_Pathname = 250 + Relative_Pathname = 251 + Pathname_Element = 252 + Base_Attribute = 253 + Subtype_Attribute = 254 + Element_Attribute = 255 + Across_Attribute = 256 + Through_Attribute = 257 + Nature_Reference_Attribute = 258 + Left_Type_Attribute = 259 + Right_Type_Attribute = 260 + High_Type_Attribute = 261 + Low_Type_Attribute = 262 + Ascending_Type_Attribute = 263 + Image_Attribute = 264 + Value_Attribute = 265 + Pos_Attribute = 266 + Val_Attribute = 267 + Succ_Attribute = 268 + Pred_Attribute = 269 + Leftof_Attribute = 270 + Rightof_Attribute = 271 + Signal_Slew_Attribute = 272 + Quantity_Slew_Attribute = 273 + Ramp_Attribute = 274 + Dot_Attribute = 275 + Integ_Attribute = 276 + Above_Attribute = 277 + Delayed_Attribute = 278 + Stable_Attribute = 279 + Quiet_Attribute = 280 + Transaction_Attribute = 281 + Event_Attribute = 282 + Active_Attribute = 283 + Last_Event_Attribute = 284 + Last_Active_Attribute = 285 + Last_Value_Attribute = 286 + Driving_Attribute = 287 + Driving_Value_Attribute = 288 + Behavior_Attribute = 289 + Structure_Attribute = 290 + Simple_Name_Attribute = 291 + Instance_Name_Attribute = 292 + Path_Name_Attribute = 293 + Left_Array_Attribute = 294 + Right_Array_Attribute = 295 + High_Array_Attribute = 296 + Low_Array_Attribute = 297 + Length_Array_Attribute = 298 + Ascending_Array_Attribute = 299 + Range_Array_Attribute = 300 + Reverse_Range_Array_Attribute = 301 + Attribute_Name = 302 class Iir_Kinds: @@ -872,7 +874,9 @@ class Iir_Kinds: Simultaneous_Statement = [ Iir_Kind.Simple_Simultaneous_Statement, + Iir_Kind.Simultaneous_Null_Statement, Iir_Kind.Simultaneous_Procedural_Statement, + Iir_Kind.Simultaneous_Case_Statement, Iir_Kind.Simultaneous_If_Statement] Concurrent_Signal_Assignment = [ diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 98d69901c..e06b795ab 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -48,7 +48,7 @@ package body Vhdl.Canon is return Iir; procedure Canon_Concurrent_Stmts (Top : Iir_Design_Unit; Parent : Iir); - procedure Canon_Simultaneous_Stmts (Top : Iir_Design_Unit; Parent : Iir); + procedure Canon_Simultaneous_Stmts (Top : Iir_Design_Unit; Chain : Iir); -- Canonicalize an association list. -- If ASSOCIATION_LIST is not null, then it is re-ordored and returned. @@ -2274,10 +2274,27 @@ package body Vhdl.Canon is if Canon_Flag_Expressions then Canon_Expression_If_Valid (Get_Condition (Clause)); end if; - Canon_Simultaneous_Stmts (Top, Clause); + Canon_Simultaneous_Stmts + (Top, Get_Simultaneous_Statement_Chain (Clause)); Clause := Get_Else_Clause (Clause); end loop; end; + when Iir_Kind_Simultaneous_Case_Statement => + declare + Alt : Iir; + begin + if Canon_Flag_Expressions then + Canon_Expression (Get_Expression (Stmt)); + end if; + Alt := Get_Case_Statement_Alternative_Chain (Stmt); + while Alt /= Null_Iir loop + if not Get_Same_Alternative_Flag (Alt) then + Canon_Simultaneous_Stmts + (Top, Get_Associated_Block (Alt)); + end if; + Alt := Get_Chain (Alt); + end loop; + end; when Iir_Kind_Simultaneous_Procedural_Statement => Canon_Declarations (Top, Stmt, Null_Iir); if Canon_Flag_Sequentials_Stmts then @@ -2289,6 +2306,8 @@ package body Vhdl.Canon is Set_Sequential_Statement_Chain (Stmt, Stmts); end; end if; + when Iir_Kind_Simultaneous_Null_Statement => + null; when others => Error_Kind ("canon_concurrent_statement", Stmt); @@ -2321,13 +2340,13 @@ package body Vhdl.Canon is end loop; end Canon_Concurrent_Stmts; - procedure Canon_Simultaneous_Stmts (Top : Iir_Design_Unit; Parent : Iir) + procedure Canon_Simultaneous_Stmts (Top : Iir_Design_Unit; Chain : Iir) is Stmt : Iir; Prev_Stmt : Iir; Proc_Num : Natural := 0; begin - Stmt := Get_Simultaneous_Statement_Chain (Parent); + Stmt := Chain; while Stmt /= Null_Iir loop Canon_Concurrent_Label (Stmt, Proc_Num); diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb index 938d5cc0f..f74fd6037 100644 --- a/src/vhdl/vhdl-elocations.adb +++ b/src/vhdl/vhdl-elocations.adb @@ -361,6 +361,7 @@ package body Vhdl.Elocations is | Iir_Kind_Case_Generate_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -477,6 +478,7 @@ package body Vhdl.Elocations is | Iir_Kind_Context_Declaration | Iir_Kind_Package_Declaration | Iir_Kind_Package_Body + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Case_Statement => return Format_L2; when Iir_Kind_Package_Instantiation_Declaration diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads index f3b0592ed..2a185341c 100644 --- a/src/vhdl/vhdl-elocations.ads +++ b/src/vhdl/vhdl-elocations.ads @@ -469,6 +469,7 @@ package Vhdl.Elocations is -- Iir_Kind_Case_Generate_Statement (None) -- Iir_Kind_Simple_Simultaneous_Statement (None) + -- Iir_Kind_Simultaneous_Null_Statement (None) -- Iir_Kind_Simultaneous_Procedural_Statement (L4) -- @@ -535,6 +536,7 @@ package Vhdl.Elocations is -- Iir_Kind_Return_Statement (None) -- Iir_Kind_Case_Statement (L2) + -- Iir_Kind_Simultaneous_Case_Statement (L2) -- -- Get/Set_End_Location (Field2) diff --git a/src/vhdl/vhdl-elocations_meta.adb b/src/vhdl/vhdl-elocations_meta.adb index ea05be130..faeae2a17 100644 --- a/src/vhdl/vhdl-elocations_meta.adb +++ b/src/vhdl/vhdl-elocations_meta.adb @@ -243,6 +243,7 @@ package body Vhdl.Elocations_Meta is | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simultaneous_Elsif | Iir_Kind_For_Loop_Statement diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index 8cdbec4ab..02dc0df5d 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -602,8 +602,12 @@ package body Vhdl.Errors is when Iir_Kind_Simple_Simultaneous_Statement => return "simple simultaneous statement"; + when Iir_Kind_Simultaneous_Null_Statement => + return "simultaneous null statement"; when Iir_Kind_Simultaneous_Procedural_Statement => return "simultaneous procedural statement"; + when Iir_Kind_Simultaneous_Case_Statement => + return "simultaneous case statement"; when Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simultaneous_Elsif => return "simultaneous if statement"; diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index 7d62b2104..84b94196d 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1136,7 +1136,9 @@ package body Vhdl.Nodes is | Iir_Kind_Psl_Default_Clock | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simultaneous_Elsif | Iir_Kind_Simple_Signal_Assignment_Statement diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c59c1c046..cb51e8920 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -531,6 +531,7 @@ package Vhdl.Nodes is -- Iir_Kind_Case_Statement -- Iir_Kind_Case_Generate_Statement -- Iir_Kind_Concurrent_Selected_Signal_Assignment + -- Iir_Kind_Simultaneous_Case_Statement -- -- The location of the first alternative is set on: -- 'when' for case statement, selected assignment and case generate, @@ -3488,6 +3489,17 @@ package Vhdl.Nodes is -- -- Get/Set_Visible_Flag (Flag4) + -- Iir_Kind_Simultaneous_Null_Statement (Short) + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Label (Field3) + -- Get/Set_Identifier (Alias Field3) + -- + -- Get/Set_Visible_Flag (Flag4) + -- Iir_Kind_Simultaneous_Procedural_Statement (Short) -- -- AMS-LRM17 11.13 Simultaneous procedural statement @@ -3560,6 +3572,28 @@ package Vhdl.Nodes is -- -- Get/Set_End_Has_Identifier (Flag9) + -- Iir_Kind_Simultaneous_Case_Statement (Short) + -- + -- Get/Set_Parent (Field0) + -- + -- Chain is composed of Iir_Kind_Choice_By_XXX. + -- Get/Set_Case_Statement_Alternative_Chain (Field1) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Label (Field3) + -- Get/Set_Identifier (Alias Field3) + -- + -- Get/Set_Expression (Field5) + -- + -- Get/Set_Visible_Flag (Flag4) + -- + -- Get/Set_Is_Within_Flag (Flag5) + -- + -- Get/Set_End_Has_Reserved_Id (Flag8) + -- + -- Get/Set_End_Has_Identifier (Flag9) + ---------------------------- -- sequential statements -- ---------------------------- @@ -4888,7 +4922,9 @@ package Vhdl.Nodes is -- Simultaneous statements. Iir_Kind_Simple_Simultaneous_Statement, + Iir_Kind_Simultaneous_Null_Statement, Iir_Kind_Simultaneous_Procedural_Statement, + Iir_Kind_Simultaneous_Case_Statement, Iir_Kind_Simultaneous_If_Statement, Iir_Kind_Simultaneous_Elsif, @@ -6301,6 +6337,9 @@ package Vhdl.Nodes is subtype Iir_Kinds_Simultaneous_Statement is Iir_Kind range Iir_Kind_Simple_Simultaneous_Statement .. + --Iir_Kind_Simultaneous_Null_Statement + --Iir_Kind_Simultaneous_Procedural_Statement + --Iir_Kind_Simultaneous_Case_Statement Iir_Kind_Simultaneous_If_Statement; subtype Iir_Kinds_Sequential_Statement is Iir_Kind range diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 206716ae7..ed955d05c 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -1533,8 +1533,12 @@ package body Vhdl.Nodes_Meta is return "if_generate_else_clause"; when Iir_Kind_Simple_Simultaneous_Statement => return "simple_simultaneous_statement"; + when Iir_Kind_Simultaneous_Null_Statement => + return "simultaneous_null_statement"; when Iir_Kind_Simultaneous_Procedural_Statement => return "simultaneous_procedural_statement"; + when Iir_Kind_Simultaneous_Case_Statement => + return "simultaneous_case_statement"; when Iir_Kind_Simultaneous_If_Statement => return "simultaneous_if_statement"; when Iir_Kind_Simultaneous_Elsif => @@ -4337,6 +4341,11 @@ package body Vhdl.Nodes_Meta is Field_Simultaneous_Left, Field_Simultaneous_Right, Field_Tolerance, + -- Iir_Kind_Simultaneous_Null_Statement + Field_Label, + Field_Visible_Flag, + Field_Parent, + Field_Chain, -- Iir_Kind_Simultaneous_Procedural_Statement Field_Label, Field_Visible_Flag, @@ -4349,6 +4358,16 @@ package body Vhdl.Nodes_Meta is Field_Declaration_Chain, Field_Attribute_Value_Chain, Field_Sequential_Statement_Chain, + -- Iir_Kind_Simultaneous_Case_Statement + Field_Label, + Field_Visible_Flag, + Field_Is_Within_Flag, + Field_End_Has_Reserved_Id, + Field_End_Has_Identifier, + Field_Parent, + Field_Case_Statement_Alternative_Chain, + Field_Chain, + Field_Expression, -- Iir_Kind_Simultaneous_If_Statement Field_Label, Field_Is_Ref, @@ -5194,92 +5213,94 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Generate_Statement_Body => 1680, Iir_Kind_If_Generate_Else_Clause => 1686, Iir_Kind_Simple_Simultaneous_Statement => 1693, - Iir_Kind_Simultaneous_Procedural_Statement => 1704, - Iir_Kind_Simultaneous_If_Statement => 1713, - Iir_Kind_Simultaneous_Elsif => 1719, - Iir_Kind_Simple_Signal_Assignment_Statement => 1730, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1741, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1753, - Iir_Kind_Null_Statement => 1757, - Iir_Kind_Assertion_Statement => 1764, - Iir_Kind_Report_Statement => 1770, - Iir_Kind_Wait_Statement => 1778, - Iir_Kind_Variable_Assignment_Statement => 1785, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1792, - Iir_Kind_Return_Statement => 1798, - Iir_Kind_For_Loop_Statement => 1809, - Iir_Kind_While_Loop_Statement => 1820, - Iir_Kind_Next_Statement => 1827, - Iir_Kind_Exit_Statement => 1834, - Iir_Kind_Case_Statement => 1842, - Iir_Kind_Procedure_Call_Statement => 1848, - Iir_Kind_Break_Statement => 1855, - Iir_Kind_If_Statement => 1865, - Iir_Kind_Elsif => 1871, - Iir_Kind_Character_Literal => 1879, - Iir_Kind_Simple_Name => 1887, - Iir_Kind_Selected_Name => 1896, - Iir_Kind_Operator_Symbol => 1902, - Iir_Kind_Reference_Name => 1907, - Iir_Kind_External_Constant_Name => 1915, - Iir_Kind_External_Signal_Name => 1923, - Iir_Kind_External_Variable_Name => 1932, - Iir_Kind_Selected_By_All_Name => 1938, - Iir_Kind_Parenthesis_Name => 1943, - Iir_Kind_Package_Pathname => 1947, - Iir_Kind_Absolute_Pathname => 1948, - Iir_Kind_Relative_Pathname => 1949, - Iir_Kind_Pathname_Element => 1954, - Iir_Kind_Base_Attribute => 1956, - Iir_Kind_Subtype_Attribute => 1961, - Iir_Kind_Element_Attribute => 1966, - Iir_Kind_Across_Attribute => 1971, - Iir_Kind_Through_Attribute => 1976, - Iir_Kind_Nature_Reference_Attribute => 1980, - Iir_Kind_Left_Type_Attribute => 1985, - Iir_Kind_Right_Type_Attribute => 1990, - Iir_Kind_High_Type_Attribute => 1995, - Iir_Kind_Low_Type_Attribute => 2000, - Iir_Kind_Ascending_Type_Attribute => 2005, - Iir_Kind_Image_Attribute => 2011, - Iir_Kind_Value_Attribute => 2017, - Iir_Kind_Pos_Attribute => 2023, - Iir_Kind_Val_Attribute => 2029, - Iir_Kind_Succ_Attribute => 2035, - Iir_Kind_Pred_Attribute => 2041, - Iir_Kind_Leftof_Attribute => 2047, - Iir_Kind_Rightof_Attribute => 2053, - Iir_Kind_Signal_Slew_Attribute => 2061, - Iir_Kind_Quantity_Slew_Attribute => 2069, - Iir_Kind_Ramp_Attribute => 2077, - Iir_Kind_Dot_Attribute => 2084, - Iir_Kind_Integ_Attribute => 2091, - Iir_Kind_Above_Attribute => 2099, - Iir_Kind_Delayed_Attribute => 2108, - Iir_Kind_Stable_Attribute => 2117, - Iir_Kind_Quiet_Attribute => 2126, - Iir_Kind_Transaction_Attribute => 2135, - Iir_Kind_Event_Attribute => 2139, - Iir_Kind_Active_Attribute => 2143, - Iir_Kind_Last_Event_Attribute => 2147, - Iir_Kind_Last_Active_Attribute => 2151, - Iir_Kind_Last_Value_Attribute => 2155, - Iir_Kind_Driving_Attribute => 2159, - Iir_Kind_Driving_Value_Attribute => 2163, - Iir_Kind_Behavior_Attribute => 2163, - Iir_Kind_Structure_Attribute => 2163, - Iir_Kind_Simple_Name_Attribute => 2170, - Iir_Kind_Instance_Name_Attribute => 2175, - Iir_Kind_Path_Name_Attribute => 2180, - Iir_Kind_Left_Array_Attribute => 2187, - Iir_Kind_Right_Array_Attribute => 2194, - Iir_Kind_High_Array_Attribute => 2201, - Iir_Kind_Low_Array_Attribute => 2208, - Iir_Kind_Length_Array_Attribute => 2215, - Iir_Kind_Ascending_Array_Attribute => 2222, - Iir_Kind_Range_Array_Attribute => 2229, - Iir_Kind_Reverse_Range_Array_Attribute => 2236, - Iir_Kind_Attribute_Name => 2245 + Iir_Kind_Simultaneous_Null_Statement => 1697, + Iir_Kind_Simultaneous_Procedural_Statement => 1708, + Iir_Kind_Simultaneous_Case_Statement => 1717, + Iir_Kind_Simultaneous_If_Statement => 1726, + Iir_Kind_Simultaneous_Elsif => 1732, + Iir_Kind_Simple_Signal_Assignment_Statement => 1743, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1754, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1766, + Iir_Kind_Null_Statement => 1770, + Iir_Kind_Assertion_Statement => 1777, + Iir_Kind_Report_Statement => 1783, + Iir_Kind_Wait_Statement => 1791, + Iir_Kind_Variable_Assignment_Statement => 1798, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1805, + Iir_Kind_Return_Statement => 1811, + Iir_Kind_For_Loop_Statement => 1822, + Iir_Kind_While_Loop_Statement => 1833, + Iir_Kind_Next_Statement => 1840, + Iir_Kind_Exit_Statement => 1847, + Iir_Kind_Case_Statement => 1855, + Iir_Kind_Procedure_Call_Statement => 1861, + Iir_Kind_Break_Statement => 1868, + Iir_Kind_If_Statement => 1878, + Iir_Kind_Elsif => 1884, + Iir_Kind_Character_Literal => 1892, + Iir_Kind_Simple_Name => 1900, + Iir_Kind_Selected_Name => 1909, + Iir_Kind_Operator_Symbol => 1915, + Iir_Kind_Reference_Name => 1920, + Iir_Kind_External_Constant_Name => 1928, + Iir_Kind_External_Signal_Name => 1936, + Iir_Kind_External_Variable_Name => 1945, + Iir_Kind_Selected_By_All_Name => 1951, + Iir_Kind_Parenthesis_Name => 1956, + Iir_Kind_Package_Pathname => 1960, + Iir_Kind_Absolute_Pathname => 1961, + Iir_Kind_Relative_Pathname => 1962, + Iir_Kind_Pathname_Element => 1967, + Iir_Kind_Base_Attribute => 1969, + Iir_Kind_Subtype_Attribute => 1974, + Iir_Kind_Element_Attribute => 1979, + Iir_Kind_Across_Attribute => 1984, + Iir_Kind_Through_Attribute => 1989, + Iir_Kind_Nature_Reference_Attribute => 1993, + Iir_Kind_Left_Type_Attribute => 1998, + Iir_Kind_Right_Type_Attribute => 2003, + Iir_Kind_High_Type_Attribute => 2008, + Iir_Kind_Low_Type_Attribute => 2013, + Iir_Kind_Ascending_Type_Attribute => 2018, + Iir_Kind_Image_Attribute => 2024, + Iir_Kind_Value_Attribute => 2030, + Iir_Kind_Pos_Attribute => 2036, + Iir_Kind_Val_Attribute => 2042, + Iir_Kind_Succ_Attribute => 2048, + Iir_Kind_Pred_Attribute => 2054, + Iir_Kind_Leftof_Attribute => 2060, + Iir_Kind_Rightof_Attribute => 2066, + Iir_Kind_Signal_Slew_Attribute => 2074, + Iir_Kind_Quantity_Slew_Attribute => 2082, + Iir_Kind_Ramp_Attribute => 2090, + Iir_Kind_Dot_Attribute => 2097, + Iir_Kind_Integ_Attribute => 2104, + Iir_Kind_Above_Attribute => 2112, + Iir_Kind_Delayed_Attribute => 2121, + Iir_Kind_Stable_Attribute => 2130, + Iir_Kind_Quiet_Attribute => 2139, + Iir_Kind_Transaction_Attribute => 2148, + Iir_Kind_Event_Attribute => 2152, + Iir_Kind_Active_Attribute => 2156, + Iir_Kind_Last_Event_Attribute => 2160, + Iir_Kind_Last_Active_Attribute => 2164, + Iir_Kind_Last_Value_Attribute => 2168, + Iir_Kind_Driving_Attribute => 2172, + Iir_Kind_Driving_Value_Attribute => 2176, + Iir_Kind_Behavior_Attribute => 2176, + Iir_Kind_Structure_Attribute => 2176, + Iir_Kind_Simple_Name_Attribute => 2183, + Iir_Kind_Instance_Name_Attribute => 2188, + Iir_Kind_Path_Name_Attribute => 2193, + Iir_Kind_Left_Array_Attribute => 2200, + Iir_Kind_Right_Array_Attribute => 2207, + Iir_Kind_High_Array_Attribute => 2214, + Iir_Kind_Low_Array_Attribute => 2221, + Iir_Kind_Length_Array_Attribute => 2228, + Iir_Kind_Ascending_Array_Attribute => 2235, + Iir_Kind_Range_Array_Attribute => 2242, + Iir_Kind_Reverse_Range_Array_Attribute => 2249, + Iir_Kind_Attribute_Name => 2258 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -8138,7 +8159,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement @@ -8995,7 +9018,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Psl_Default_Clock | Iir_Kind_Generate_Statement_Body | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement @@ -9050,7 +9075,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement @@ -9149,7 +9176,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_If_Generate_Else_Clause | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement @@ -10164,6 +10193,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Allocator_By_Expression | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Case_Generate_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement | Iir_Kind_Variable_Assignment_Statement | Iir_Kind_Return_Statement @@ -10456,7 +10486,9 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Generate_Statement_Body | Iir_Kind_If_Generate_Else_Clause | Iir_Kind_Simple_Simultaneous_Statement + | Iir_Kind_Simultaneous_Null_Statement | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simultaneous_Elsif | Iir_Kind_Simple_Signal_Assignment_Statement @@ -11301,6 +11333,7 @@ package body Vhdl.Nodes_Meta is begin case K is when Iir_Kind_Case_Generate_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Case_Statement => return True; when others => @@ -11516,6 +11549,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_For_Generate_Statement | Iir_Kind_Generate_Statement_Body | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_For_Loop_Statement => return True; when others => @@ -11640,7 +11674,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement | Iir_Kind_For_Generate_Statement - | Iir_Kind_Simultaneous_Procedural_Statement => + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement => return True; when others => return False; @@ -11676,6 +11711,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_For_Generate_Statement | Iir_Kind_Generate_Statement_Body | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Simultaneous_Case_Statement | Iir_Kind_Simultaneous_If_Statement | Iir_Kind_Simultaneous_Elsif | Iir_Kind_For_Loop_Statement diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 3ec1777a2..81c5a7b37 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -77,6 +77,8 @@ package body Vhdl.Parse is Label_Loc : Location_Type; If_Loc : Location_Type; First_Cond : Iir) return Iir; + function Parse_Simultaneous_Case_Statement + (Label : Name_Id; Loc : Location_Type; Expr : Iir) return Iir; -- Maximum number of nested parenthesis, before generating an error. Max_Parenthesis_Depth : constant Natural := 1000; @@ -7337,8 +7339,7 @@ package body Vhdl.Parse is Set_Expression (Stmt, Parse_Expression); -- Skip 'is'. - Expect (Tok_Is); - Scan; + Expect_Scan (Tok_Is); if Current_Token = Tok_End then Error_Msg_Parse ("missing alternative in case statement"); @@ -9000,18 +9001,31 @@ package body Vhdl.Parse is Res : Iir; Alt : Iir; Last_Alt : Iir; + Expr : Iir; + Start_Loc : Location_Type; begin + Start_Loc := Get_Token_Location; + + -- Skip 'case'. + Scan; + + Expr := Parse_Expression; + + if Current_Token = Tok_Use then + if not AMS_Vhdl then + Error_Msg_Parse ("if/use is an AMS-VHDL statement"); + end if; + return Parse_Simultaneous_Case_Statement (Label, Loc, Expr); + end if; + if Label = Null_Identifier then - Error_Msg_Parse ("a generate statement must have a label"); + Error_Msg_Parse (Start_Loc, "a generate statement must have a label"); end if; + Res := Create_Iir (Iir_Kind_Case_Generate_Statement); Set_Location (Res, Loc); Set_Label (Res, Label); - - -- Skip 'case'. - Scan; - - Set_Expression (Res, Parse_Expression); + Set_Expression (Res, Expr); -- Skip 'generate' Expect_Scan (Tok_Generate); @@ -9131,6 +9145,28 @@ package body Vhdl.Parse is return Res; end Parse_Simultaneous_Procedural_Statement; + -- precond : NULL + -- + -- AMS-LRM17 11.14 Simultaneous null statement + -- simultaneous_null_statement ::= + -- [ label : ] NULL ; + function Parse_Simultaneous_Null_Statement + (Label : Name_Id; Loc : Location_Type) return Iir + is + Res : Iir; + begin + Res := Create_Iir (Iir_Kind_Simultaneous_Null_Statement); + Set_Location (Res, Loc); + Set_Label (Res, Label); + + -- Skip 'procedural'. + Scan; + + Scan_Semi_Colon_Declaration ("null statement"); + + return Res; + end Parse_Simultaneous_Null_Statement; + -- precond : first token -- postcond: next token -- @@ -9264,16 +9300,16 @@ package body Vhdl.Parse is -- -- simultaneous_statement_part ::= -- { simultaneous_statement } - procedure Parse_Simultaneous_Statements (Parent : Iir) + function Parse_Simultaneous_Statements (Parent : Iir) return Iir is - Last_Stmt : Iir; + First_Stmt, Last_Stmt : Iir; Stmt: Iir; Label: Name_Id; Loc : Location_Type; Start_Loc : Location_Type; Expr : Iir; begin - Last_Stmt := Null_Iir; + Chain_Init (First_Stmt, Last_Stmt); loop Stmt := Null_Iir; Label := Null_Identifier; @@ -9307,7 +9343,7 @@ package body Vhdl.Parse is if Label /= Null_Identifier then Error_Msg_Parse ("label is not allowed here"); end if; - return; + return First_Stmt; when Tok_Identifier => -- FIXME: sign, factor, parenthesis... Expr := Parse_Name (Allow_Indexes => True); @@ -9322,9 +9358,18 @@ package body Vhdl.Parse is Stmt := Parse_Simultaneous_If_Statement (Label, Loc, Start_Loc, Expr); + when Tok_Case => + -- Skip 'case'. + Scan; + + Expr := Parse_Expression; + + Stmt := Parse_Simultaneous_Case_Statement (Label, Loc, Expr); + when Tok_Null => + Stmt := Parse_Simultaneous_Null_Statement (Label, Loc); when Tok_Eof => Error_Msg_Parse ("unexpected end of file, 'END;' expected"); - return; + return First_Stmt; when others => -- FIXME: improve message: Unexpected ("simultaneous statement list"); @@ -9344,12 +9389,7 @@ package body Vhdl.Parse is end if; Set_Parent (Stmt, Parent); -- Append it to the chain. - if Last_Stmt = Null_Iir then - Set_Simultaneous_Statement_Chain (Parent, Stmt); - else - Set_Chain (Last_Stmt, Stmt); - end if; - Last_Stmt := Stmt; + Chain_Append (First_Stmt, Last_Stmt, Stmt); end if; end loop; end Parse_Simultaneous_Statements; @@ -9391,7 +9431,8 @@ package body Vhdl.Parse is Expect_Error (Tok_Use, "'use' is expected here"); end if; - Parse_Simultaneous_Statements (Clause); + Set_Simultaneous_Statement_Chain + (Clause, Parse_Simultaneous_Statements (Clause)); End_Loc := Get_Token_Location; @@ -9414,7 +9455,8 @@ package body Vhdl.Parse is -- Skip 'else'. Scan; - Parse_Simultaneous_Statements (Clause); + Set_Simultaneous_Statement_Chain + (Clause, Parse_Simultaneous_Statements (Clause)); if Flag_Elocations then Create_Elocations (Clause); @@ -9441,6 +9483,63 @@ package body Vhdl.Parse is return Res; end Parse_Simultaneous_If_Statement; + -- simultaneous_case_statement ::= + -- /case/_label : + -- CASE expression USE + -- simultaneous_alternative + -- { simultaneous_alternative } + -- END CASE [ /case/_label ] ; + function Parse_Simultaneous_Case_Statement + (Label : Name_Id; Loc : Location_Type; Expr : Iir) return Iir + is + Res : Iir; + When_Loc : Location_Type; + Assoc : Iir; + First_Assoc, Last_Assoc : Iir; + begin + Res := Create_Iir (Iir_Kind_Simultaneous_Case_Statement); + Set_Location (Res, Loc); + Set_Label (Res, Label); + Set_Expression (Res, Expr); + + -- Skip 'use' + Expect_Scan (Tok_Use); + + if Current_Token = Tok_End then + Error_Msg_Parse ("no generate alternative"); + end if; + + Chain_Init (First_Assoc, Last_Assoc); + while Current_Token = Tok_When loop + When_Loc := Get_Token_Location; + + -- Skip 'when'. + Scan; + + Parse_Choices (Null_Iir, When_Loc, Assoc); + + -- Skip '=>'. + Expect_Scan (Tok_Double_Arrow); + + Set_Associated_Chain (Assoc, Parse_Simultaneous_Statements (Res)); + Chain_Append_Subchain (First_Assoc, Last_Assoc, Assoc); + end loop; + + Set_Case_Statement_Alternative_Chain (Res, First_Assoc); + + -- Skip 'end', 'case' + Expect_Scan (Tok_End); + Expect_Scan (Tok_Case); + + -- LRM93 9.7 + -- If a label appears at the end of a generate statement, it must repeat + -- the generate label. + Check_End_Name (Res); + Expect_Scan (Tok_Semi_Colon); + + return Res; + end Parse_Simultaneous_Case_Statement; + -- Parse end of PSL assert/cover statement. procedure Parse_Psl_Assert_Report_Severity (Stmt : Iir; Flag_Psl : Boolean) is @@ -9684,9 +9783,6 @@ package body Vhdl.Parse is when Tok_Case => Postponed_Not_Allowed; Stmt := Parse_Case_Generate_Statement (Label, Loc); - when Tok_Eof => - Error_Msg_Parse ("unexpected end of file, 'END;' expected"); - return; when Tok_Component | Tok_Entity | Tok_Configuration => @@ -9706,6 +9802,13 @@ package body Vhdl.Parse is when Tok_Procedural => Postponed_Not_Allowed; Stmt := Parse_Simultaneous_Procedural_Statement (Label); + when Tok_Null => + if not AMS_Vhdl then + Error_Msg_Parse ("concurrent null statement not allowed"); + else + Postponed_Not_Allowed; + end if; + Stmt := Parse_Simultaneous_Null_Statement (Label, Loc); when Tok_Default => Postponed_Not_Allowed; Label_Not_Allowed; @@ -9732,6 +9835,9 @@ package body Vhdl.Parse is ("sequential statement only allowed in processes"); Stmt := Parse_Sequential_Statements (Parent); Stmt := Null_Iir; + when Tok_Eof => + Error_Msg_Parse ("unexpected end of file, 'END;' expected"); + return; when others => -- FIXME: improve message: -- instead of 'unexpected token 'signal' in conc stmt list' diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index b8513d28e..af230fe83 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -57,7 +57,7 @@ package body Vhdl.Prints is procedure Disp_Concurrent_Statement_Chain (Ctxt : in out Ctxt_Class; Parent: Iir); procedure Disp_Simultaneous_Statement_Chain - (Ctxt : in out Ctxt_Class; Parent: Iir); + (Ctxt : in out Ctxt_Class; Chain: Iir); procedure Disp_Declaration_Chain (Ctxt : in out Ctxt_Class; Parent : Iir); procedure Disp_Process_Statement (Ctxt : in out Ctxt_Class; Process: Iir); @@ -1377,11 +1377,11 @@ package body Vhdl.Prints is end Disp_Concurrent_Statement_Chain; procedure Disp_Simultaneous_Statement_Chain - (Ctxt : in out Ctxt_Class; Parent : Iir) + (Ctxt : in out Ctxt_Class; Chain : Iir) is El: Iir; begin - El := Get_Simultaneous_Statement_Chain (Parent); + El := Chain; while El /= Null_Iir loop Disp_Concurrent_Statement (Ctxt, El); El := Get_Chain (El); @@ -3784,43 +3784,6 @@ package body Vhdl.Prints is Disp_End (Ctxt, Stmt, Tok_Generate); end Disp_Case_Generate_Statement; - procedure Disp_Simultaneous_If_Statement - (Ctxt : in out Ctxt_Class; Stmt : Iir) - is - Clause : Iir; - Expr : Iir; - begin - Start_Hbox (Ctxt); - Disp_Label (Ctxt, Stmt); - Disp_Token (Ctxt, Tok_If); - Clause := Stmt; - Print (Ctxt, Get_Condition (Clause)); - Close_Hbox (Ctxt); - Start_Hbox (Ctxt); - Disp_Token (Ctxt, Tok_Use); - Close_Hbox (Ctxt); - while Clause /= Null_Iir loop - Start_Vbox (Ctxt); - Disp_Simultaneous_Statement_Chain (Ctxt, Clause); - Close_Vbox (Ctxt); - Clause := Get_Else_Clause (Clause); - exit when Clause = Null_Iir; - Start_Hbox (Ctxt); - Expr := Get_Condition (Clause); - if Expr /= Null_Iir then - Disp_Token (Ctxt, Tok_Elsif); - Print (Ctxt, Expr); - Close_Hbox (Ctxt); - Start_Hbox (Ctxt); - Disp_Token (Ctxt, Tok_Use); - else - Disp_Token (Ctxt, Tok_Else); - end if; - Close_Hbox (Ctxt); - end loop; - Disp_End_Label (Ctxt, Stmt, Tok_Use); - end Disp_Simultaneous_If_Statement; - procedure Disp_PSL_NFA (Ctxt : in out Ctxt_Class; N : PSL.Nodes.NFA) is use PSL.NFAs; @@ -3945,6 +3908,78 @@ package body Vhdl.Prints is Close_Hbox (Ctxt); end Disp_Simple_Simultaneous_Statement; + procedure Disp_Simultaneous_If_Statement + (Ctxt : in out Ctxt_Class; Stmt : Iir) + is + Clause : Iir; + Expr : Iir; + begin + Start_Hbox (Ctxt); + Disp_Label (Ctxt, Stmt); + Disp_Token (Ctxt, Tok_If); + Clause := Stmt; + Print (Ctxt, Get_Condition (Clause)); + Close_Hbox (Ctxt); + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_Use); + Close_Hbox (Ctxt); + while Clause /= Null_Iir loop + Start_Vbox (Ctxt); + Disp_Simultaneous_Statement_Chain + (Ctxt, Get_Simultaneous_Statement_Chain (Clause)); + Close_Vbox (Ctxt); + Clause := Get_Else_Clause (Clause); + exit when Clause = Null_Iir; + Start_Hbox (Ctxt); + Expr := Get_Condition (Clause); + if Expr /= Null_Iir then + Disp_Token (Ctxt, Tok_Elsif); + Print (Ctxt, Expr); + Close_Hbox (Ctxt); + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_Use); + else + Disp_Token (Ctxt, Tok_Else); + end if; + Close_Hbox (Ctxt); + end loop; + Disp_End_Label (Ctxt, Stmt, Tok_Use); + end Disp_Simultaneous_If_Statement; + + procedure Disp_Simultaneous_Case_Statement + (Ctxt : in out Ctxt_Class; Stmt : Iir) + is + Assoc: Iir; + Stmts : Iir; + begin + Start_Hbox (Ctxt); + Disp_Label (Ctxt, Stmt); + Disp_Token (Ctxt, Tok_Case); + Print (Ctxt, Get_Expression (Stmt)); + Close_Hbox (Ctxt); + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_Use); + Close_Hbox (Ctxt); + + Start_Vbox (Ctxt); + Assoc := Get_Case_Statement_Alternative_Chain (Stmt); + while Assoc /= Null_Iir loop + Start_Hbox (Ctxt); + Disp_Token (Ctxt, Tok_When); + Stmts := Get_Associated_Chain (Assoc); + Disp_Choice (Ctxt, Assoc); + Disp_Token (Ctxt, Tok_Double_Arrow); + Close_Hbox (Ctxt); + + Start_Vbox (Ctxt); + Disp_Simultaneous_Statement_Chain (Ctxt, Stmts); + Close_Vbox (Ctxt); + end loop; + Close_Vbox (Ctxt); + + Disp_End_Label (Ctxt, Stmt, Tok_Case); + end Disp_Simultaneous_Case_Statement; + procedure Disp_Simultaneous_Procedural_Statement (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin @@ -3977,6 +4012,16 @@ package body Vhdl.Prints is Close_Hbox (Ctxt); end Disp_Simultaneous_Procedural_Statement; + procedure Disp_Simultaneous_Null_Statement + (Ctxt : in out Ctxt_Class; Stmt : Iir) is + begin + Start_Hbox (Ctxt); + Disp_Label (Ctxt, Stmt); + Disp_Token (Ctxt, Tok_Null); + Disp_Token (Ctxt, Tok_Semi_Colon); + Close_Hbox (Ctxt); + end Disp_Simultaneous_Null_Statement; + procedure Disp_Concurrent_Statement (Ctxt : in out Ctxt_Class; Stmt: Iir) is begin case Get_Kind (Stmt) is @@ -4022,8 +4067,12 @@ package body Vhdl.Prints is Disp_Simple_Simultaneous_Statement (Ctxt, Stmt); when Iir_Kind_Simultaneous_If_Statement => Disp_Simultaneous_If_Statement (Ctxt, Stmt); + when Iir_Kind_Simultaneous_Case_Statement => + Disp_Simultaneous_Case_Statement (Ctxt, Stmt); when Iir_Kind_Simultaneous_Procedural_Statement => Disp_Simultaneous_Procedural_Statement (Ctxt, Stmt); + when Iir_Kind_Simultaneous_Null_Statement => + Disp_Simultaneous_Null_Statement (Ctxt, Stmt); when others => Error_Kind ("disp_concurrent_statement", Stmt); end case; diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 43b41d16a..befb9b2fa 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -2167,6 +2167,32 @@ package body Vhdl.Sem_Stmts is end loop; end Sem_Simultaneous_If_Statement; + procedure Sem_Simultaneous_Case_Statement (Stmt : Iir) + is + Expr: Iir; + Chain : Iir; + El: Iir; + begin + Expr := Get_Expression (Stmt); + Expr := Sem_Case_Expression (Expr); + if Expr /= Null_Iir then + Check_Read (Expr); + Set_Expression (Stmt, Expr); + + Chain := Get_Case_Statement_Alternative_Chain (Stmt); + Sem_Case_Choices (Expr, Chain, Get_Location (Stmt)); + Set_Case_Statement_Alternative_Chain (Stmt, Chain); + end if; + + El := Chain; + while El /= Null_Iir loop + if not Get_Same_Alternative_Flag (El) then + Sem_Simultaneous_Statements (Get_Associated_Chain (El)); + end if; + El := Get_Chain (El); + end loop; + end Sem_Simultaneous_Case_Statement; + procedure Sem_Simultaneous_Procedural_Statement (Stmt : Iir) is begin Set_Is_Within_Flag (Stmt, True); @@ -2193,8 +2219,12 @@ package body Vhdl.Sem_Stmts is Sem_Simple_Simultaneous_Statement (Stmt); when Iir_Kind_Simultaneous_If_Statement => Sem_Simultaneous_If_Statement (Stmt); + when Iir_Kind_Simultaneous_Case_Statement => + Sem_Simultaneous_Case_Statement (Stmt); when Iir_Kind_Simultaneous_Procedural_Statement => Sem_Simultaneous_Procedural_Statement (Stmt); + when Iir_Kind_Simultaneous_Null_Statement => + null; when others => Error_Kind ("sem_simultaneous_statements", Stmt); end case; @@ -2276,8 +2306,12 @@ package body Vhdl.Sem_Stmts is Sem_Simple_Simultaneous_Statement (Stmt); when Iir_Kind_Simultaneous_If_Statement => Sem_Simultaneous_If_Statement (Stmt); + when Iir_Kind_Simultaneous_Case_Statement => + Sem_Simultaneous_Case_Statement (Stmt); when Iir_Kind_Simultaneous_Procedural_Statement => Sem_Simultaneous_Procedural_Statement (Stmt); + when Iir_Kind_Simultaneous_Null_Statement => + null; when others => Error_Kind ("sem_concurrent_statement", Stmt); end case; |