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-rw-r--r--testsuite/synth/issue1144/issue.vhdl14
-rwxr-xr-xtestsuite/synth/issue1144/testsuite.sh11
2 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/issue1144/issue.vhdl b/testsuite/synth/issue1144/issue.vhdl
new file mode 100644
index 000000000..ca9721b75
--- /dev/null
+++ b/testsuite/synth/issue1144/issue.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue is
+ port (i_data : in std_logic_vector(8 downto 0);
+ o_data : out std_logic_vector(3 downto 0);
+ clock : in std_logic);
+end issue;
+
+architecture rtl of issue is
+ alias i_hi is i_data(3 downto 0);
+begin
+ o_data <= i_hi;
+end architecture;
diff --git a/testsuite/synth/issue1144/testsuite.sh b/testsuite/synth/issue1144/testsuite.sh
new file mode 100755
index 000000000..ce1265354
--- /dev/null
+++ b/testsuite/synth/issue1144/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in issue; do
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl
+ clean
+done
+
+echo "Test successful"