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-rwxr-xr-xtestsuite/gna/issue1067/testsuite.sh20
-rw-r--r--testsuite/gna/issue1067/top.vhdl16
2 files changed, 36 insertions, 0 deletions
diff --git a/testsuite/gna/issue1067/testsuite.sh b/testsuite/gna/issue1067/testsuite.sh
new file mode 100755
index 000000000..edba5bba5
--- /dev/null
+++ b/testsuite/gna/issue1067/testsuite.sh
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+for f in top; do
+ analyze $f.vhdl
+ elab $f
+
+ if ghdl_has_feature $f ghw; then
+ simulate $f --dump-rti
+ simulate $f --wave=$f.ghw
+ rm -f $f.ghw
+ fi
+done
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue1067/top.vhdl b/testsuite/gna/issue1067/top.vhdl
new file mode 100644
index 000000000..52df2196f
--- /dev/null
+++ b/testsuite/gna/issue1067/top.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity top is
+end entity ;
+
+architecture arch_top of top is
+
+ type t_slv_array is array(natural range <>) of std_logic_vector;
+
+ signal test : t_slv_array(0 to 2)(7 downto 0);
+
+begin
+
+end architecture arch_top;