diff options
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-values.adb | 10 | ||||
| -rw-r--r-- | src/synth/synth-values.ads | 7 |
4 files changed, 26 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index e97f3ff5a..6685d71ae 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -649,6 +649,10 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= std_logic_vector (resize (\ui0 * \ui1, \n0));" & NL, Inst, (0 => Get_Width (Get_Output (Inst, 0)))); + when Id_Smul => + Disp_Template + (" \o0 <= std_logic_vector (resize (\si0 * \si1, \n0));" & NL, + Inst, (0 => Get_Width (Get_Output (Inst, 0)))); when Id_Ult => Disp_Template (" \o0 <= '1' when \ui0 < \ui1 else '0';" & NL, Inst); diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index b68637498..8c58adafc 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -920,6 +920,9 @@ package body Synth.Expr is when Type_Vector => -- TODO: check width return Val; + when Type_Slice => + -- TODO: check width + return Val; when Type_Array => -- TODO: check bounds, handle elements return Val; @@ -1914,7 +1917,8 @@ package body Synth.Expr is Inp, Step, Off, Wd); Set_Location (N, Name); -- TODO: the bounds cannot be created as they are not known. - return Create_Value_Net (N, null); + Res_Type := Create_Slice_Type (Wd, Pfx.Typ.Vec_El); + return Create_Value_Net (N, Res_Type); else N := Build_Extract (Build_Context, Get_Net (Pfx), Uns32 (Off), Wd); Set_Location (N, Name); diff --git a/src/synth/synth-values.adb b/src/synth/synth-values.adb index e199d8698..b7179e695 100644 --- a/src/synth/synth-values.adb +++ b/src/synth/synth-values.adb @@ -129,6 +129,16 @@ package body Synth.Values is Vec_El => El_Type))); end Create_Vector_Type; + function Create_Slice_Type (W : Width; El_Type : Type_Acc) return Type_Acc + is + subtype Slice_Type_Type is Type_Type (Type_Slice); + function Alloc is new Areapools.Alloc_On_Pool_Addr (Slice_Type_Type); + begin + return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Slice, + W => W, + Slice_El => El_Type))); + end Create_Slice_Type; + function Create_Vec_Type_By_Length (Len : Width; El : Type_Acc) return Type_Acc is diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads index fa6f0908f..9d2026270 100644 --- a/src/synth/synth-values.ads +++ b/src/synth/synth-values.ads @@ -76,6 +76,10 @@ package Synth.Values is Type_Discrete, Type_Float, Type_Vector, + + -- A slice is for a slice of vector with dynamic bounds. So the bounds + -- of the result aren't known, but its width is. + Type_Slice, Type_Array, Type_Unbounded_Array, Type_Record @@ -108,6 +112,8 @@ package Synth.Values is when Type_Vector => Vbound : Bound_Type; Vec_El : Type_Acc; + when Type_Slice => + Slice_El : Type_Acc; when Type_Array => Abounds : Bound_Array_Acc; Arr_El : Type_Acc; @@ -219,6 +225,7 @@ package Synth.Values is return Type_Acc; function Create_Vector_Type (Bnd : Bound_Type; El_Type : Type_Acc) return Type_Acc; + function Create_Slice_Type (W : Width; El_Type : Type_Acc) return Type_Acc; function Create_Bound_Array (Ndims : Iir_Index32) return Bound_Array_Acc; function Create_Array_Type (Bnd : Bound_Array_Acc; El_Type : Type_Acc) return Type_Acc; |