diff options
-rw-r--r-- | src/synth/netlists-cleanup.adb | 28 | ||||
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 30 | ||||
-rw-r--r-- | src/synth/synth-insts.adb | 33 |
3 files changed, 46 insertions, 45 deletions
diff --git a/src/synth/netlists-cleanup.adb b/src/synth/netlists-cleanup.adb index deec7186b..0a4fb3dc1 100644 --- a/src/synth/netlists-cleanup.adb +++ b/src/synth/netlists-cleanup.adb @@ -126,18 +126,22 @@ package body Netlists.Cleanup is while Inst /= No_Instance loop Next_Inst := Get_Next_Instance (Inst); - if Get_Id (Inst) = Id_Output then - Inp := Get_Input (Inst, 0); - O := Get_Driver (Inp); - if O /= No_Net then - -- Only when the output is driven. - Disconnect (Inp); - Redirect_Inputs (Get_Output (Inst, 0), O); - else - Disconnect (Get_First_Sink (Get_Output (Inst, 0))); - end if; - Remove_Instance (Inst); - end if; + case Get_Id (Inst) is + when Id_Output + | Id_Port => + Inp := Get_Input (Inst, 0); + O := Get_Driver (Inp); + if O /= No_Net then + -- Only when the output is driven. + Disconnect (Inp); + Redirect_Inputs (Get_Output (Inst, 0), O); + else + Disconnect (Get_First_Sink (Get_Output (Inst, 0))); + end if; + Remove_Instance (Inst); + when others => + null; + end case; Inst := Next_Inst; end loop; diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 67d51d552..eae711c57 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -128,23 +128,25 @@ package body Netlists.Disp_Vhdl is declare Inst : constant Instance := Get_Net_Parent (N); Idx : constant Port_Idx := Get_Port_Idx (N); + M : Module; Inst_Name : Sname; Port_Name : Sname; begin if Is_Self_Instance (Inst) then + -- For ports of the current module, simply use the port name. Put_Name (Get_Input_Desc (Get_Module (Inst), Idx).Name); else Inst_Name := Get_Instance_Name (Inst); Put_Name (Inst_Name); - case Get_Sname_Kind (Inst_Name) is - when Sname_Version => - Port_Name := Get_Output_Desc (Get_Module (Inst), Idx).Name; - Put ("_"); - Put_Interface_Name (Port_Name); - when Sname_User => + M := Get_Module (Inst); + case Get_Id (M) is + when Id_Signal + | Id_Isignal => null; when others => - raise Internal_Error; + Port_Name := Get_Output_Desc (M, Idx).Name; + Put ("_"); + Put_Interface_Name (Port_Name); end case; end if; end; @@ -227,20 +229,12 @@ package body Netlists.Disp_Vhdl is Put (" => "); declare I : Input; - O_Inst : Instance; begin I := Get_First_Sink (O); if I = No_Input then Put ("open"); else - O_Inst := Get_Input_Parent (I); - if O_Inst /= No_Instance - and then Get_Id (O_Inst) = Id_Port - then - Disp_Net_Name (Get_Output (O_Inst, 0)); - else - Disp_Net_Name (O); - end if; + Disp_Net_Name (O); end if; end; end loop; @@ -763,7 +757,7 @@ package body Netlists.Disp_Vhdl is when Id_Isignal => Disp_Template (" \o0 <= \i0; -- (isignal)" & NL, Inst); when Id_Port => - null; + Disp_Template (" \o0 <= \i0; -- (port)" & NL, Inst); when Id_Not => Disp_Template (" \o0 <= not \i0;" & NL, Inst); when Id_Neg => @@ -1174,8 +1168,8 @@ package body Netlists.Disp_Vhdl is if not Is_Self_Instance (Inst) and then not (Flag_Merge_Lit and then Id in Constant_Module_Id + and then Id < Id_User_None and then not Need_Signal (Inst)) - and then Id < Id_User_None then for N of Outputs (Inst) loop if Id in Constant_Module_Id then diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 4c9f72fd0..3e2fd6b3d 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -32,7 +32,7 @@ with Synthesis; use Synthesis; with Grt.Algos; with Netlists; use Netlists; -with Netlists.Builders; +with Netlists.Builders; use Netlists.Builders; with Netlists.Cleanup; with Netlists.Memories; with Netlists.Expands; @@ -597,7 +597,6 @@ package body Synth.Insts is Assoc : Node; Inter_Inst : Synth_Instance_Acc) is - use Netlists.Builders; Iassoc : Node; V : Value_Acc; Off : Uns32; @@ -930,7 +929,8 @@ package body Synth.Insts is (Syn_Inst, Stmt, Comp, Null_Node, Null_Node); end Synth_Blackbox_Instantiation_Statement; - procedure Create_Component_Wire (Inter : Node; Val : Value_Acc) + procedure Create_Component_Wire + (Ctxt : Context_Acc; Inter : Node; Val : Value_Acc; Pfx_Name : Sname) is Value : Net; W : Width; @@ -940,9 +940,8 @@ package body Synth.Insts is -- Create a gate for the output, so that it could be read. Val.W := Alloc_Wire (Wire_Output, Inter); W := Get_Type_Width (Val.Typ); - Value := Builders.Build_Signal - (Build_Context, - New_Sname_User (Get_Identifier (Inter), No_Sname), W); + Value := Build_Signal + (Ctxt, New_Internal_Name (Ctxt, Pfx_Name), W); Set_Wire_Gate (Val.W, Value); when others => raise Internal_Error; @@ -965,10 +964,14 @@ package body Synth.Insts is Sub_Inst : Synth_Instance_Acc; Inst_Obj : Inst_Object; Inst : Instance; + Inst_Name : Sname; begin pragma Assert (Get_Component_Configuration (Stmt) /= Null_Node); pragma Assert (Get_Kind (Aspect) = Iir_Kind_Entity_Aspect_Entity); + Inst_Name := New_Sname_User (Get_Identifier (Stmt), + Get_Sname (Syn_Inst)); + -- Create the sub-instance for the component -- Elaborate generic + map aspect Comp_Inst := Make_Instance @@ -979,7 +982,8 @@ package body Synth.Insts is Get_Generic_Chain (Component), Get_Generic_Map_Aspect_Chain (Stmt)); - -- Create objects for inputs and outputs, assign inputs. + -- Create objects for the inputs and the outputs of the component, + -- assign inputs (that's nets) and create wires for outputs. declare Assoc : Node; Assoc_Inter : Node; @@ -1010,7 +1014,8 @@ package body Synth.Insts is (Syn_Inst, Actual, Inter_Type); when Port_Out => Val := Create_Value_Wire (No_Wire_Id, Inter_Type); - Create_Component_Wire (Assoc_Inter, Val); + Create_Component_Wire + (Get_Build (Syn_Inst), Assoc_Inter, Val, Inst_Name); end case; Create_Object (Comp_Inst, Assoc_Inter, Val); Next_Association_Interface (Assoc, Assoc_Inter); @@ -1060,9 +1065,7 @@ package body Synth.Insts is -- TODO: free sub_inst. Inst := New_Instance (Get_Instance_Module (Syn_Inst), - Inst_Obj.M, - New_Sname_User (Get_Identifier (Stmt), - Get_Sname (Syn_Inst))); + Inst_Obj.M, Inst_Name); Synth_Instantiate_Module (Comp_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Bind)); @@ -1100,10 +1103,10 @@ package body Synth.Insts is null; when Port_Out => if Actual /= Null_Node then - Port := Get_Output (Inst, Nbr_Outputs); - Port := Builders.Build_Port (Get_Build (Syn_Inst), Port); - O := Create_Value_Net - (Port, Get_Value (Comp_Inst, Inter).Typ); + O := Get_Value (Comp_Inst, Inter); + Port := Get_Net (O); + Port := Build_Port (Get_Build (Syn_Inst), Port); + O := Create_Value_Net (Port, O.Typ); Synth_Assignment (Syn_Inst, Actual, O, Assoc); end if; Nbr_Outputs := Nbr_Outputs + 1; |