diff options
| -rw-r--r-- | doc/appendix/Meta.rst | 2 | ||||
| -rw-r--r-- | doc/references/ImplementationOfVHDL.rst | 2 | ||||
| -rw-r--r-- | doc/using/InvokingGHDL.rst | 20 | ||||
| -rw-r--r-- | doc/using/QuickStartGuide.rst | 6 | ||||
| -rw-r--r-- | doc/using/Simulation.rst | 2 |
5 files changed, 16 insertions, 16 deletions
diff --git a/doc/appendix/Meta.rst b/doc/appendix/Meta.rst index 2430e6f45..5a95f1793 100644 --- a/doc/appendix/Meta.rst +++ b/doc/appendix/Meta.rst @@ -55,7 +55,7 @@ General guidelines to edit the documentation ToC entry <file1> file2 - 7) Documentation should not use “you”, “we”, …, because it’s not an interactive conversation or informal letter. It’s like a thesis, everything is structured and formal. However, to make it more friendly to newcomers, we agree to allow informal language in the section ':ref:`USING:QuickStart`'. + 7) Documentation should not use “you”, “we”, …, because it’s not an interactive conversation or informal letter. It’s like a thesis, everything is structured and formal. However, to make it more friendly to newcomers, we agree to allow informal language in the section :ref:`USING:QuickStart`. 8) Please keep errors to a minimum. diff --git a/doc/references/ImplementationOfVHDL.rst b/doc/references/ImplementationOfVHDL.rst index 0169d7ad8..3cb766e2c 100644 --- a/doc/references/ImplementationOfVHDL.rst +++ b/doc/references/ImplementationOfVHDL.rst @@ -324,7 +324,7 @@ Linking with foreign object files --------------------------------- You may add additional files or options during the link using the -*-Wl,* of `GHDL`, as described in ':ref:`Elaboration:command`'. +*-Wl,* of `GHDL`, as described in :ref:`Elaboration:command`. For example:: ghdl -e -Wl,-lm math_tb diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst index f857563c5..de018d949 100644 --- a/doc/using/InvokingGHDL.rst +++ b/doc/using/InvokingGHDL.rst @@ -39,7 +39,7 @@ Analysis [``-a``] Analyzes/compiles one or more files, and creates an object file for each source file. Any argument starting with a dash is an option, the others are filenames. No options are allowed after a filename argument. GHDL analyzes each filename in the given order, and stops the analysis in case of error (remaining files are not analyzed). -See ':ref:`GHDL:options`', for details on the GHDL options. For example, to produce debugging information such as line numbers, use: ``ghdl -a -g my_design.vhdl``. +See :ref:`GHDL:options`, for details on the GHDL options. For example, to produce debugging information such as line numbers, use: ``ghdl -a -g my_design.vhdl``. .. index:: cmd elaboration @@ -59,7 +59,7 @@ Re-analyzes all the configurations, entities, architectures and package declarat * an entity unit * an entity unit followed by a name of an architecture unit -Name of the units must be a simple name, without any dot. You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in ':ref:`GHDL:options`'. See section ':ref:`Top_entity`', for the restrictions on the root design of a hierarchy. +Name of the units must be a simple name, without any dot. You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL:options`. See section :ref:`Top_entity`, for the restrictions on the root design of a hierarchy. * If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the latter case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename. @@ -84,7 +84,7 @@ This command exists for three reasons: * It is coherent with the :option:`-a` and :option:`-e` commands. * It works with mcode implementation, where the executable code is generated in memory. -See section ':ref:`USING:Simulation`', for details on options. +See section :ref:`USING:Simulation`, for details on options. .. index:: cmd elaborate and run @@ -232,7 +232,7 @@ Options .. option:: --std<=STD> - Specify the standard to use. By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax. For details on ``STD`` values see section ':ref:`VHDL_standards`'. + Specify the standard to use. By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax. For details on ``STD`` values see section :ref:`VHDL_standards`. .. option:: --ieee<=VER> @@ -254,7 +254,7 @@ Options packages ``numeric_bit`` and ``numeric_std`` defined by IEEE 1076.3, and the ``vital`` packages ``vital_timing`` and ``vital_primitives``, defined by IEEE 1076.4. The version of these - packages is defined by the VHDL standard used. See section ':ref:`VITAL_packages`', + packages is defined by the VHDL standard used. See section :ref:`VITAL_packages`, for more details. synopsys @@ -289,7 +289,7 @@ Options When two operators are overloaded, give preference to the explicit declaration. This may be used to avoid the most common pitfall of the ``std_logic_arith`` - package. See section ':ref:`IEEE_library_pitfalls`', for an example. + package. See section :ref:`IEEE_library_pitfalls`, for an example. .. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule. When set, an operator can be silently overridden in another package. You'd do better to fix your design and use the ``numeric_std`` package. @@ -316,7 +316,7 @@ Options .. option:: -fpsl - Enable parsing of PSL assertions within comments. See section ':ref:`PSL_implementation`' for more details. + Enable parsing of PSL assertions within comments. See section :ref:`PSL_implementation` for more details. .. option:: --no-vital-checks .. option:: --vital-checks @@ -325,7 +325,7 @@ Options Checks are performed only when a design unit is decorated by a VITAL attribute. The VITAL attributes are ``VITAL_Level0`` and ``VITAL_Level1``, both declared in the ``ieee.VITAL_Timing`` package. - Currently, VITAL checks are only partially implemented. See section ':ref:`VHDL_restrictions_for_VITAL`' for more details. + Currently, VITAL checks are only partially implemented. See section :ref:`VHDL_restrictions_for_VITAL` for more details. .. option:: --PREFIX<=PATH> @@ -350,7 +350,7 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag .. option:: --warn-default-binding - During analyze, warns if a component instantiation has neither configuration specification nor default binding. This may be useful if you want to detect during analyze possibly unbound components if you don't use configuration. See section ':ref:`VHDL_standards`' for more details about default binding rules. + During analyze, warns if a component instantiation has neither configuration specification nor default binding. This may be useful if you want to detect during analyze possibly unbound components if you don't use configuration. See section :ref:`VHDL_standards` for more details about default binding rules. .. option:: --warn-binding @@ -632,7 +632,7 @@ Indeed, the `"="` operator is defined in both packages, and both are visible at With some analysers, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error. However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules, it emits an error. -You can force GHDL to use this rule with the *-fexplicit* option (see ':ref:`GHDL:options`' for further details). However it is easy to fix this error, by using a selected name: +You can force GHDL to use this rule with the *-fexplicit* option (see :ref:`GHDL:options` for further details). However it is easy to fix this error, by using a selected name: .. code-block:: VHDL diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst index c332e58c3..9dbe84bdf 100644 --- a/doc/using/QuickStartGuide.rst +++ b/doc/using/QuickStartGuide.rst @@ -168,11 +168,11 @@ Now, it is time to run the testbench, ``ghdl -r adder_tb``, and check the result adder_tb.vhdl:52:7:(assertion note): end of test -If your design is rather complex, you'd like to inspect signals. Signal values can be dumped using multiple formats (see section ':ref:`export_waves`' for more information). The resulting file can be read with a wave viewer such as `GtkWave <http://gtkwave.sourceforge.net/>`_. +If your design is rather complex, you'd like to inspect signals. Signal values can be dumped using multiple formats (see section :ref:`export_waves` for more information). The resulting file can be read with a wave viewer such as `GtkWave <http://gtkwave.sourceforge.net/>`_. As explained in the `manual <http://gtkwave.sourceforge.net/gtkwave.pdf>`_, GtkWave *'relies on a post-mortem approach through the use of dumpfiles'*. Therefore, you should first simulate your design and dump a waveform file, say VCD: ``ghdl -r adder_tb --vcd=adder.vcd``. Then, you can view the dump: ``gtkwave adder.vcd``. -See section ':ref:`simulation_options`', for more details on other runtime options. +See section :ref:`simulation_options`, for more details on other runtime options. Starting with a design ====================== @@ -215,4 +215,4 @@ Unless you are only studying VHDL, you will work with larger designs than the on * Remove the design library with the GHDL command ``ghdl --remove --workdir=work``. This removes the executable, all the object files and the library file. If you want to rebuild the design, you have to import the sources again and make the design. * Remove the :file:`work/` directory: ``rm -rf work``. Only the executable is kept. If you want to rebuild the design, create the :file:`work/` directory, import the sources, and make the design. -.. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it might use the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details. +.. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it might use the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section :ref:`IEEE_library_pitfalls`, for more details. diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst index 5eb624262..570c184af 100644 --- a/doc/using/Simulation.rst +++ b/doc/using/Simulation.rst @@ -100,7 +100,7 @@ all options available, including the debugging one. typical or maximum values. If the option does not contain a type of delay, the annotator uses the typical delay. - See section ':ref:`Backannotation`', for more details. + See section :ref:`Backannotation`, for more details. .. option:: --vpi<=FILENAME> |