diff options
| -rw-r--r-- | src/synth/synth-environment-debug.adb | 31 | ||||
| -rw-r--r-- | src/synth/synth-environment-debug.ads | 9 | ||||
| -rw-r--r-- | src/synth/synth-environment.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-values-debug.adb | 9 |
4 files changed, 35 insertions, 20 deletions
diff --git a/src/synth/synth-environment-debug.adb b/src/synth/synth-environment-debug.adb index 3278e8ba9..96cdf5981 100644 --- a/src/synth/synth-environment-debug.adb +++ b/src/synth/synth-environment-debug.adb @@ -21,12 +21,20 @@ with Ada.Text_IO; use Ada.Text_IO; with Netlists.Dump; use Netlists.Dump; +with Synth.Values.Debug; use Synth.Values.Debug; + package body Synth.Environment.Debug is - procedure Dump_Wire (Wid : Wire_Id) + procedure Put_Wire_Id (Wid : Wire_Id) is + begin + Put (Wire_Id'Image (Wid)); + end Put_Wire_Id; + + procedure Debug_Wire (Wid : Wire_Id) is W_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid); begin - Put ("Wire:" & Wire_Id'Image (Wid)); + Put ("Wire:"); + Put_Wire_Id (Wid); Put_Line (" kind: " & Wire_Kind'Image (W_Rec.Kind)); Put_Line (" decl:" & Source.Syn_Src'Image (W_Rec.Decl)); Put (" gate: "); @@ -34,7 +42,7 @@ package body Synth.Environment.Debug is New_Line; Put_Line (" cur_assign:" & Seq_Assign'Image (W_Rec.Cur_Assign)); Put_Line (" conc_assign:" & Conc_Assign'Image(W_Rec.Final_Assign)); - end Dump_Wire; + end Debug_Wire; procedure Dump_Partial_Assign (Pasgn : Partial_Assign) is @@ -65,7 +73,7 @@ package body Synth.Environment.Debug is end loop; end Dump_Partial_Assign; - procedure Dump_Assign (Asgn : Seq_Assign) + procedure Debug_Assign (Asgn : Seq_Assign) is Rec : Seq_Assign_Record renames Assign_Table.Table (Asgn); begin @@ -88,13 +96,14 @@ package body Synth.Environment.Debug is when Unknown => Put_Line (" ??? (unknown)"); when True => - Put_Line (" static"); + Put_Line (" static:"); + Debug_Memtyp (Rec.Val.Val); when False => Dump_Partial_Assign (Rec.Val.Asgns); end case; - end Dump_Assign; + end Debug_Assign; - procedure Dump_Phi (Id : Phi_Id) + procedure Debug_Phi (Id : Phi_Id) is Phi : Phi_Type renames Phis_Table.Table (Id); Asgn : Seq_Assign; @@ -103,12 +112,12 @@ package body Synth.Environment.Debug is New_Line; Asgn := Phi.First; while Asgn /= No_Seq_Assign loop - Dump_Assign (Asgn); + Debug_Assign (Asgn); Asgn := Get_Assign_Chain (Asgn); end loop; - end Dump_Phi; + end Debug_Phi; - procedure Dump_Conc_Assigns (First : Conc_Assign) + procedure Debug_Conc_Assigns (First : Conc_Assign) is Asgn : Conc_Assign; begin @@ -127,5 +136,5 @@ package body Synth.Environment.Debug is end; New_Line; end loop; - end Dump_Conc_Assigns; + end Debug_Conc_Assigns; end Synth.Environment.Debug; diff --git a/src/synth/synth-environment-debug.ads b/src/synth/synth-environment-debug.ads index 074608e2a..9fd81b42c 100644 --- a/src/synth/synth-environment-debug.ads +++ b/src/synth/synth-environment-debug.ads @@ -19,9 +19,10 @@ -- MA 02110-1301, USA. package Synth.Environment.Debug is - procedure Dump_Wire (Wid : Wire_Id); - procedure Dump_Assign (Asgn : Seq_Assign); - procedure Dump_Conc_Assigns (First : Conc_Assign); + procedure Put_Wire_Id (Wid : Wire_Id); + procedure Debug_Wire (Wid : Wire_Id); + procedure Debug_Assign (Asgn : Seq_Assign); + procedure Debug_Conc_Assigns (First : Conc_Assign); private - procedure Dump_Phi (Id : Phi_Id); + procedure Debug_Phi (Id : Phi_Id); end Synth.Environment.Debug; diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index d6bb29883..a48ae0119 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -1315,7 +1315,7 @@ package body Synth.Environment is end Merge_Partial_Assigns; procedure Merge_Assigns (Ctxt : Builders.Context_Acc; - W : Wire_Id; + Wid : Wire_Id; Sel : Net; F_Asgns : Seq_Assign_Value; T_Asgns : Seq_Assign_Value; @@ -1347,7 +1347,7 @@ package body Synth.Environment is for I in N'Range loop if N (I) = No_Net then -- No partial assignment. Get extract previous value. - N (I) := Get_Current_Assign_Value (Ctxt, W, Off, Wd); + N (I) := Get_Current_Assign_Value (Ctxt, Wid, Off, Wd); end if; end loop; @@ -1407,7 +1407,7 @@ package body Synth.Environment is -- Do the assignments from the result list. -- It cannot be done before because the assignments will overwrite the -- last assignments which are read to create a partial assignment. - Merge_Partial_Assigns (Ctxt, W, List); + Merge_Partial_Assigns (Ctxt, Wid, List); end Merge_Assigns; function Merge_Static_Assigns (Wid : Wire_Id; Tv, Fv : Seq_Assign_Value) diff --git a/src/synth/synth-values-debug.adb b/src/synth/synth-values-debug.adb index 493c30e7e..2e3e111c1 100644 --- a/src/synth/synth-values-debug.adb +++ b/src/synth/synth-values-debug.adb @@ -20,8 +20,11 @@ with Simple_IO; use Simple_IO; with Utils_IO; use Utils_IO; + with Vhdl.Nodes; use Vhdl.Nodes; +with Synth.Environment.Debug; use Synth.Environment.Debug; + package body Synth.Values.Debug is procedure Put_Dir (Dir : Direction_Type) is begin @@ -178,9 +181,11 @@ package body Synth.Values.Debug is | Value_Const => Debug_Memtyp (Get_Memtyp (V)); when Value_Net => - Put_Line ("a net"); + Put_Line (" net"); when Value_Wire => - Put_Line ("a wire"); + Put (" wire"); + Put_Wire_Id (V.Val.W); + New_Line; when Value_File => Put_Line ("a file"); when Value_Alias => |